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7e157b0ade
If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>
101 lines
3 KiB
C
101 lines
3 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef DDR2_DIMM_PARAMS_H
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#define DDR2_DIMM_PARAMS_H
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#define EDC_DATA_PARITY 1
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#define EDC_ECC 2
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#define EDC_AC_PARITY 4
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/* Parameters for a DDR2 dimm computed from the SPD */
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typedef struct dimm_params_s {
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/* DIMM organization parameters */
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char mpart[19]; /* guaranteed null terminated */
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unsigned int n_ranks;
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unsigned long long rank_density;
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unsigned long long capacity;
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unsigned int data_width;
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unsigned int primary_sdram_width;
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unsigned int ec_sdram_width;
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unsigned int registered_dimm;
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unsigned int device_width; /* x4, x8, x16 components */
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/* SDRAM device parameters */
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unsigned int n_row_addr;
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unsigned int n_col_addr;
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unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
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unsigned int n_banks_per_sdram_device;
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unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
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unsigned int row_density;
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/* used in computing base address of DIMMs */
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unsigned long long base_address;
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/* mirrored DIMMs */
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unsigned int mirrored_dimm; /* only for ddr3 */
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/* DIMM timing parameters */
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unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */
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unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */
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unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */
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unsigned int tfaw_ps; /* four active window delay, only for ddr3 */
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/*
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* SDRAM clock periods
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* The range for these are 1000-10000 so a short should be sufficient
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*/
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unsigned int tckmin_x_ps;
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unsigned int tckmin_x_minus_1_ps;
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unsigned int tckmin_x_minus_2_ps;
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unsigned int tckmax_ps;
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/* SPD-defined CAS latencies */
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unsigned int caslat_x;
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unsigned int caslat_x_minus_1;
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unsigned int caslat_x_minus_2;
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unsigned int caslat_lowest_derated; /* Derated CAS latency */
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/* basic timing parameters */
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unsigned int trcd_ps;
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unsigned int trp_ps;
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unsigned int tras_ps;
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unsigned int twr_ps; /* maximum = 63750 ps */
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unsigned int twtr_ps; /* maximum = 63750 ps */
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unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns
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= 511750 ps */
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unsigned int trrd_ps; /* maximum = 63750 ps */
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unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
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unsigned int refresh_rate_ps;
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unsigned int extended_op_srt;
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/* DDR3 doesn't need these as below */
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unsigned int tis_ps; /* byte 32, spd->ca_setup */
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unsigned int tih_ps; /* byte 33, spd->ca_hold */
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unsigned int tds_ps; /* byte 34, spd->data_setup */
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unsigned int tdh_ps; /* byte 35, spd->data_hold */
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unsigned int trtp_ps; /* byte 38, spd->trtp */
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unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */
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unsigned int tqhs_ps; /* byte 45, spd->tqhs */
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/* DDR3 RDIMM */
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unsigned char rcw[16]; /* Register Control Word 0-15 */
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} dimm_params_t;
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extern unsigned int ddr_compute_dimm_parameters(
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const generic_spd_eeprom_t *spd,
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dimm_params_t *pdimm,
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unsigned int dimm_number);
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#endif
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