mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
4dfb2196cd
When using dual boot mode, the DDR won't be reset when APD power off or reboot. It has possibility that obsolete fdt data existing on fdt_addr_r address. Then even nothing in EFI partitions, the distro boot still continue to parse fdt and get uboot crashed. Clear the data at fdt_addr_r, so the fdt header check in above case will not pass. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/imx8ulp-pins.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pcc.h>
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#include <asm/arch/sys_proto.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE)
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static iomux_cfg_t const enet_clk_pads[] = {
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IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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};
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static int setup_fec(void)
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{
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/*
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* Since ref clock and timestamp clock are from external,
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* set the iomux prior the clock enablement
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*/
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imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads));
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/* Select enet time stamp clock: 001 - External Timestamp Clock */
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cgc1_enet_stamp_sel(1);
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/* enable FEC PCC */
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pcc_clock_enable(4, ENET_PCC4_SLOT, true);
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pcc_reset_peripheral(4, ENET_PCC4_SLOT, false);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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#define I2C_PAD_CTRL (PAD_CTL_ODE)
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static const iomux_cfg_t lpi2c0_pads[] = {
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IMX8ULP_PAD_PTA8__LPI2C0_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
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IMX8ULP_PAD_PTA9__LPI2C0_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
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};
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#define TPM_PAD_CTRL (PAD_CTL_DSE)
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static const iomux_cfg_t tpm0_pads[] = {
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IMX8ULP_PAD_PTA3__TPM0_CH2 | MUX_PAD_CTRL(TPM_PAD_CTRL),
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};
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void mipi_dsi_mux_panel(void)
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{
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int ret;
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struct gpio_desc desc;
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/* It is temp solution to directly access i2c, need change to rpmsg later */
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/* enable lpi2c0 clock and iomux */
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imx8ulp_iomux_setup_multiple_pads(lpi2c0_pads, ARRAY_SIZE(lpi2c0_pads));
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writel(0xD2000000, 0x28091060);
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ret = dm_gpio_lookup_name("gpio@20_9", &desc);
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if (ret) {
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printf("%s lookup gpio@20_9 failed ret = %d\n", __func__, ret);
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return;
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}
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ret = dm_gpio_request(&desc, "dsi_mux");
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if (ret) {
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printf("%s request dsi_mux failed ret = %d\n", __func__, ret);
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return;
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}
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dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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}
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void mipi_dsi_panel_backlight(void)
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{
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/* It is temp solution to directly access pwm, need change to rpmsg later */
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imx8ulp_iomux_setup_multiple_pads(tpm0_pads, ARRAY_SIZE(tpm0_pads));
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writel(0xD4000001, 0x28091054);
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/* Use center-aligned PWM mode, CPWMS=1, MSnB:MSnA = 10, ELSnB:ELSnA = 00 */
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writel(1000, 0x28095018);
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writel(1000, 0x28095034); /* MOD = CV, full duty */
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writel(0x28, 0x28095010);
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writel(0x20, 0x28095030);
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}
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int board_init(void)
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{
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if (IS_ENABLED(CONFIG_FEC_MXC))
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setup_fec();
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/* When sync with M33 is failed, use local driver to set for video */
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if (!is_m33_handshake_necessary() && IS_ENABLED(CONFIG_VIDEO)) {
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mipi_dsi_mux_panel();
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mipi_dsi_panel_backlight();
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}
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return 0;
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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ulong addr;
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#if CONFIG_IS_ENABLED(ENV_IS_IN_MMC)
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board_late_mmc_env_init();
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#endif
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/* clear fdtaddr to avoid obsolete data */
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addr = env_get_hex("fdt_addr_r", 0);
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if (addr)
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memset((void *)addr, 0, 0x400);
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return 0;
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}
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