mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
7208396bbf
This reverts commit5d3a21df66, reversing changes made to56d37f1c56. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
640 lines
16 KiB
C
640 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2009 Michal Simek
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* (C) Copyright 2003 Xilinx Inc.
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*
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* Michal SIMEK <monstr@monstr.eu>
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*/
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#include <common.h>
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#include <log.h>
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#include <net.h>
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#include <config.h>
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#include <dm.h>
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#include <console.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <fdtdec.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ENET_ADDR_LENGTH 6
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#define ETH_FCS_LEN 4 /* Octets in the FCS */
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/* Xmit complete */
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#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
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/* Xmit interrupt enable bit */
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#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
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/* Program the MAC address */
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#define XEL_TSR_PROGRAM_MASK 0x00000002UL
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/* define for programming the MAC address into the EMAC Lite */
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#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
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/* Transmit packet length upper byte */
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#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
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/* Transmit packet length lower byte */
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#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
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/* Recv complete */
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#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
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/* Recv interrupt enable bit */
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#define XEL_RSR_RECV_IE_MASK 0x00000008UL
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/* MDIO Address Register Bit Masks */
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#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
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#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
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#define XEL_MDIOADDR_PHYADR_SHIFT 5
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#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
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/* MDIO Write Data Register Bit Masks */
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#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
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/* MDIO Read Data Register Bit Masks */
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#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
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/* MDIO Control Register Bit Masks */
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#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
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#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
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struct emaclite_regs {
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u32 tx_ping; /* 0x0 - TX Ping buffer */
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u32 reserved1[504];
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u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
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u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
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u32 mdiord;/* 0x7ec - MDIO Read Data Register */
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u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
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u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
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u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
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u32 tx_ping_tsr; /* 0x7fc - Tx status */
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u32 tx_pong; /* 0x800 - TX Pong buffer */
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u32 reserved2[508];
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u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
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u32 reserved3; /* 0xff8 */
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u32 tx_pong_tsr; /* 0xffc - Tx status */
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u32 rx_ping; /* 0x1000 - Receive Buffer */
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u32 reserved4[510];
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u32 rx_ping_rsr; /* 0x17fc - Rx status */
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u32 rx_pong; /* 0x1800 - Receive Buffer */
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u32 reserved5[510];
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u32 rx_pong_rsr; /* 0x1ffc - Rx status */
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};
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struct xemaclite {
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bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
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u32 txpp; /* TX ping pong buffer */
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u32 rxpp; /* RX ping pong buffer */
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int phyaddr;
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struct emaclite_regs *regs;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
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static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
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{
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u32 i;
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u32 alignbuffer;
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u32 *to32ptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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/* Word aligned buffer, no correction needed. */
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to32ptr = (u32 *) destptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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to8ptr = (u8 *) to32ptr;
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alignbuffer = *from32ptr++;
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from8ptr = (u8 *) &alignbuffer;
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for (i = 0; i < bytecount; i++)
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*to8ptr++ = *from8ptr++;
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}
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static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
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{
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u32 i;
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u32 alignbuffer;
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u32 *to32ptr = (u32 *) destptr;
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u32 *from32ptr;
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u8 *to8ptr;
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u8 *from8ptr;
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from32ptr = (u32 *) srcptr;
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while (bytecount > 3) {
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*to32ptr++ = *from32ptr++;
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bytecount -= 4;
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}
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alignbuffer = 0;
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to8ptr = (u8 *) &alignbuffer;
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from8ptr = (u8 *) from32ptr;
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for (i = 0; i < bytecount; i++)
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*to8ptr++ = *from8ptr++;
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*to32ptr++ = alignbuffer;
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}
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static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
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bool set, unsigned int timeout)
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{
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u32 val;
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unsigned long start = get_timer(0);
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while (1) {
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val = __raw_readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout)
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break;
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if (ctrlc()) {
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puts("Abort\n");
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return -EINTR;
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}
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udelay(1);
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}
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
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func, reg, mask, set);
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return -ETIMEDOUT;
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}
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static int mdio_wait(struct emaclite_regs *regs)
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{
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return wait_for_bit(__func__, ®s->mdioctrl,
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XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
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}
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static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
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u16 *data)
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{
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struct emaclite_regs *regs = emaclite->regs;
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if (mdio_wait(regs))
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return 1;
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u32 ctrl_reg = __raw_readl(®s->mdioctrl);
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__raw_writel(XEL_MDIOADDR_OP_MASK
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| ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
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| registernum), ®s->mdioaddr);
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__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
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if (mdio_wait(regs))
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return 1;
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/* Read data */
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*data = __raw_readl(®s->mdiord);
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return 0;
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}
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static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
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u16 data)
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{
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struct emaclite_regs *regs = emaclite->regs;
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if (mdio_wait(regs))
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return 1;
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/*
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* Write the PHY address, register number and clear the OP bit in the
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* MDIO Address register and then write the value into the MDIO Write
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* Data register. Finally, set the Status bit in the MDIO Control
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* register to start a MDIO write transaction.
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*/
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u32 ctrl_reg = __raw_readl(®s->mdioctrl);
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__raw_writel(~XEL_MDIOADDR_OP_MASK
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& ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
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| registernum), ®s->mdioaddr);
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__raw_writel(data, ®s->mdiowr);
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__raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
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if (mdio_wait(regs))
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return 1;
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return 0;
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}
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static void emaclite_stop(struct udevice *dev)
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{
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debug("eth_stop\n");
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}
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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static int setup_phy(struct udevice *dev)
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{
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int i, ret;
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u16 phyreg;
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struct xemaclite *emaclite = dev_get_priv(dev);
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struct phy_device *phydev;
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u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full;
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if (emaclite->phyaddr != -1) {
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phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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debug("Default phy address %d is valid\n",
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emaclite->phyaddr);
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} else {
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debug("PHY address is not setup correctly %d\n",
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emaclite->phyaddr);
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emaclite->phyaddr = -1;
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}
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}
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if (emaclite->phyaddr == -1) {
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/* detect the PHY address */
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for (i = 31; i >= 0; i--) {
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phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
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if ((phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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emaclite->phyaddr = i;
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debug("emaclite: Found valid phy address, %d\n",
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i);
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break;
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}
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}
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}
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/* interface - look at tsec */
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phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
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PHY_INTERFACE_MODE_MII);
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/*
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* Phy can support 1000baseT but device NOT that's why phydev->supported
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* must be setup for 1000baseT. phydev->advertising setups what speeds
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* will be used for autonegotiation where 1000baseT must be disabled.
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*/
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phydev->supported = supported | SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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phydev->advertising = supported;
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emaclite->phydev = phydev;
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phy_config(phydev);
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ret = phy_startup(phydev);
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if (ret)
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return ret;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return 0;
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}
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/* Do not setup anything */
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return 1;
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}
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static int emaclite_start(struct udevice *dev)
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{
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struct xemaclite *emaclite = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct emaclite_regs *regs = emaclite->regs;
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debug("EmacLite Initialization Started\n");
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/*
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* TX - TX_PING & TX_PONG initialization
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*/
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/* Restart PING TX */
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__raw_writel(0, ®s->tx_ping_tsr);
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/* Copy MAC address */
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xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
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ENET_ADDR_LENGTH);
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/* Set the length */
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__raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
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/* Update the MAC address in the EMAC Lite */
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__raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
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/* Wait for EMAC Lite to finish with the MAC address update */
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while ((__raw_readl(®s->tx_ping_tsr) &
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XEL_TSR_PROG_MAC_ADDR) != 0)
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;
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if (emaclite->txpp) {
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/* The same operation with PONG TX */
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__raw_writel(0, ®s->tx_pong_tsr);
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xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
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ENET_ADDR_LENGTH);
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__raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
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__raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
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while ((__raw_readl(®s->tx_pong_tsr) &
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XEL_TSR_PROG_MAC_ADDR) != 0)
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;
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}
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/*
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* RX - RX_PING & RX_PONG initialization
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*/
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/* Write out the value to flush the RX buffer */
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__raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
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if (emaclite->rxpp)
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__raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
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__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
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if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
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if (!setup_phy(dev))
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return -1;
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debug("EmacLite Initialization complete\n");
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return 0;
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}
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static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
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{
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u32 tmp;
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struct emaclite_regs *regs = emaclite->regs;
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/*
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* Read the other buffer register
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* and determine if the other buffer is available
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*/
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tmp = ~__raw_readl(®s->tx_ping_tsr);
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if (emaclite->txpp)
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tmp |= ~__raw_readl(®s->tx_pong_tsr);
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return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
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}
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static int emaclite_send(struct udevice *dev, void *ptr, int len)
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{
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u32 reg;
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struct xemaclite *emaclite = dev_get_priv(dev);
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struct emaclite_regs *regs = emaclite->regs;
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u32 maxtry = 1000;
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if (len > PKTSIZE)
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len = PKTSIZE;
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while (xemaclite_txbufferavailable(emaclite) && maxtry) {
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udelay(10);
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maxtry--;
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}
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if (!maxtry) {
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printf("Error: Timeout waiting for ethernet TX buffer\n");
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/* Restart PING TX */
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__raw_writel(0, ®s->tx_ping_tsr);
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if (emaclite->txpp) {
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__raw_writel(0, ®s->tx_pong_tsr);
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}
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return -1;
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}
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/* Determine if the expected buffer address is empty */
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reg = __raw_readl(®s->tx_ping_tsr);
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if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
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debug("Send packet from tx_ping buffer\n");
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/* Write the frame to the buffer */
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xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
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__raw_writel(len
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& (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
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®s->tx_ping_tplr);
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reg = __raw_readl(®s->tx_ping_tsr);
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reg |= XEL_TSR_XMIT_BUSY_MASK;
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__raw_writel(reg, ®s->tx_ping_tsr);
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return 0;
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}
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if (emaclite->txpp) {
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/* Determine if the expected buffer address is empty */
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reg = __raw_readl(®s->tx_pong_tsr);
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if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
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debug("Send packet from tx_pong buffer\n");
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/* Write the frame to the buffer */
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xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
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__raw_writel(len &
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(XEL_TPLR_LENGTH_MASK_HI |
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XEL_TPLR_LENGTH_MASK_LO),
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®s->tx_pong_tplr);
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reg = __raw_readl(®s->tx_pong_tsr);
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reg |= XEL_TSR_XMIT_BUSY_MASK;
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__raw_writel(reg, ®s->tx_pong_tsr);
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return 0;
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}
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}
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puts("Error while sending frame\n");
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return -1;
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}
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static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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u32 length, first_read, reg, attempt = 0;
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void *addr, *ack;
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struct xemaclite *emaclite = dev->priv;
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struct emaclite_regs *regs = emaclite->regs;
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struct ethernet_hdr *eth;
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struct ip_udp_hdr *ip;
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try_again:
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if (!emaclite->use_rx_pong_buffer_next) {
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reg = __raw_readl(®s->rx_ping_rsr);
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debug("Testing data at rx_ping\n");
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if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
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debug("Data found in rx_ping buffer\n");
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addr = ®s->rx_ping;
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ack = ®s->rx_ping_rsr;
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} else {
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debug("Data not found in rx_ping buffer\n");
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/* Pong buffer is not available - return immediately */
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if (!emaclite->rxpp)
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return -1;
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|
/* Try pong buffer if this is first attempt */
|
|
if (attempt++)
|
|
return -1;
|
|
emaclite->use_rx_pong_buffer_next =
|
|
!emaclite->use_rx_pong_buffer_next;
|
|
goto try_again;
|
|
}
|
|
} else {
|
|
reg = __raw_readl(®s->rx_pong_rsr);
|
|
debug("Testing data at rx_pong\n");
|
|
if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
|
|
debug("Data found in rx_pong buffer\n");
|
|
addr = ®s->rx_pong;
|
|
ack = ®s->rx_pong_rsr;
|
|
} else {
|
|
debug("Data not found in rx_pong buffer\n");
|
|
/* Try ping buffer if this is first attempt */
|
|
if (attempt++)
|
|
return -1;
|
|
emaclite->use_rx_pong_buffer_next =
|
|
!emaclite->use_rx_pong_buffer_next;
|
|
goto try_again;
|
|
}
|
|
}
|
|
|
|
/* Read all bytes for ARP packet with 32bit alignment - 48bytes */
|
|
first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
|
|
xemaclite_alignedread(addr, etherrxbuff, first_read);
|
|
|
|
/* Detect real packet size */
|
|
eth = (struct ethernet_hdr *)etherrxbuff;
|
|
switch (ntohs(eth->et_protlen)) {
|
|
case PROT_ARP:
|
|
length = first_read;
|
|
debug("ARP Packet %x\n", length);
|
|
break;
|
|
case PROT_IP:
|
|
ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
|
|
length = ntohs(ip->ip_len);
|
|
length += ETHER_HDR_SIZE + ETH_FCS_LEN;
|
|
debug("IP Packet %x\n", length);
|
|
break;
|
|
default:
|
|
debug("Other Packet\n");
|
|
length = PKTSIZE;
|
|
break;
|
|
}
|
|
|
|
/* Read the rest of the packet which is longer then first read */
|
|
if (length != first_read)
|
|
xemaclite_alignedread(addr + first_read,
|
|
etherrxbuff + first_read,
|
|
length - first_read);
|
|
|
|
/* Acknowledge the frame */
|
|
reg = __raw_readl(ack);
|
|
reg &= ~XEL_RSR_RECV_DONE_MASK;
|
|
__raw_writel(reg, ack);
|
|
|
|
debug("Packet receive from 0x%p, length %dB\n", addr, length);
|
|
*packetp = etherrxbuff;
|
|
return length;
|
|
}
|
|
|
|
static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
|
|
int devad, int reg)
|
|
{
|
|
u32 ret;
|
|
u16 val = 0;
|
|
|
|
ret = phyread(bus->priv, addr, reg, &val);
|
|
debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
|
|
return val;
|
|
}
|
|
|
|
static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
|
|
int reg, u16 value)
|
|
{
|
|
debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
|
|
return phywrite(bus->priv, addr, reg, value);
|
|
}
|
|
|
|
static int emaclite_probe(struct udevice *dev)
|
|
{
|
|
struct xemaclite *emaclite = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
emaclite->bus = mdio_alloc();
|
|
emaclite->bus->read = emaclite_miiphy_read;
|
|
emaclite->bus->write = emaclite_miiphy_write;
|
|
emaclite->bus->priv = emaclite;
|
|
|
|
ret = mdio_register_seq(emaclite->bus, dev->seq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int emaclite_remove(struct udevice *dev)
|
|
{
|
|
struct xemaclite *emaclite = dev_get_priv(dev);
|
|
|
|
free(emaclite->phydev);
|
|
mdio_unregister(emaclite->bus);
|
|
mdio_free(emaclite->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops emaclite_ops = {
|
|
.start = emaclite_start,
|
|
.send = emaclite_send,
|
|
.recv = emaclite_recv,
|
|
.stop = emaclite_stop,
|
|
};
|
|
|
|
static int emaclite_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct xemaclite *emaclite = dev_get_priv(dev);
|
|
int offset = 0;
|
|
|
|
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
|
|
emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
|
|
0x10000);
|
|
|
|
emaclite->phyaddr = -1;
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
|
|
"phy-handle");
|
|
if (offset > 0)
|
|
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
|
|
"reg", -1);
|
|
|
|
emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
|
"xlnx,tx-ping-pong", 0);
|
|
emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
|
|
"xlnx,rx-ping-pong", 0);
|
|
|
|
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
|
|
emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id emaclite_ids[] = {
|
|
{ .compatible = "xlnx,xps-ethernetlite-1.00.a" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(emaclite) = {
|
|
.name = "emaclite",
|
|
.id = UCLASS_ETH,
|
|
.of_match = emaclite_ids,
|
|
.ofdata_to_platdata = emaclite_ofdata_to_platdata,
|
|
.probe = emaclite_probe,
|
|
.remove = emaclite_remove,
|
|
.ops = &emaclite_ops,
|
|
.priv_auto_alloc_size = sizeof(struct xemaclite),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|