mirror of
https://github.com/AsahiLinux/u-boot
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7194ab8095
All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111 - cleaned up line lengths - modified all boards that override weak function in this driver - modified all eeprom standalone apps to work with new driver - updated blackfin standalone EEPROM app after testing Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Logic LH7A400-10 card engine
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*/
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#ifndef __LPD7A404_10_H
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#define __LPD7A404_10_H
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#define CONFIG_ARM920T 1 /* arm920t core */
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#define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */
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#define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */
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/* The system clock PLL input frequency */
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#define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */
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/* ticks per second */
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#define CONFIG_SYS_HZ (508469)
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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* The stack sizes are set up in start.S using the settings below
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#ifdef CONFIG_USE_IRQ
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#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
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#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
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#endif
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
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#define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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/*----------------------------------------------------------------------
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* Using SMC91C111 LAN chip
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*
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* Default IO base of chip is 0x300, Card Engine has this address lines
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* (LAN chip) tied to Vcc, so we just care about the chip select
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_SMC91111
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#define CONFIG_SMC91111_BASE (0x70000000)
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#undef CONFIG_SMC_USE_32_BIT
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#define CONFIG_SMC_USE_IOFUNCS
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#endif /* __LPD7A404_10_H */
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