mirror of
https://github.com/AsahiLinux/u-boot
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4893e34b00
This converts the following to Kconfig: CONFIG_CMD_BSP Signed-off-by: Simon Glass <sjg@chromium.org>
247 lines
8.8 KiB
C
247 lines
8.8 KiB
C
/*
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* (C) Copyright 2003
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* Denis Peter d.peter@mpl.ch
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* File: PATI.h
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
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#define CONFIG_PATI 1 /* ...On a PATI board */
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#define CONFIG_SYS_TEXT_BASE 0xFFF00000
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/* Serial Console Configuration */
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#define CONFIG_5xx_CONS_SCI1
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#undef CONFIG_5xx_CONS_SCI2
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_IRQ
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#define CONFIG_BOOTCOMMAND "" /* autoboot command */
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#define CONFIG_BOOTARGS "" /* */
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#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
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#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_PREBOOT
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
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/***********************************************************************
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* Last Stage Init
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***********************************************************************/
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#define CONFIG_LAST_STAGE_INIT
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/*
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* Low Level Configuration Settings
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*/
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/*
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* Internal Memory Mapped (This is not the IMMR content)
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*/
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#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
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/*
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* Definitions for initial stack pointer and data area
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
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#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
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/*
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* Start addresses for the final memory configuration
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
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#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
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#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
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#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
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#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
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#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
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/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
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/* This adress is given to the linker with -Ttext to */
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/* locate the text section at this adress. */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_ENV_IS_IN_EEPROM
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_ENV_OFFSET 0
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#define CONFIG_ENV_SIZE 2048
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#endif
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#undef CONFIG_ENV_IS_IN_FLASH
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
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#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
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#endif
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#define CONFIG_SPI 1
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#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
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#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
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#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* SW Watchdog freeze
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*/
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#undef CONFIG_WATCHDOG
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWP)
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#endif /* CONFIG_WATCHDOG */
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK SCCR_EBDF00
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#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
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SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration
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*-----------------------------------------------------------------------
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* Data show cycle
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register
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*-----------------------------------------------------------------------
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* Set all bits to 40 Mhz
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*
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*/
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#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
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#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
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/*-----------------------------------------------------------------------
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* UMCR - UIMB Module Configuration Register
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*-----------------------------------------------------------------------
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*
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*/
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#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
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/*-----------------------------------------------------------------------
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* ICTRL - I-Bus Support Control Register
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*/
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#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
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/*-----------------------------------------------------------------------
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* USIU - Memory Controller Register
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
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#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
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/* SDRAM */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
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#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
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/* PCI */
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#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
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#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
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/* config registers: */
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#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
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#define CONFIG_SYS_OR3_PRELIM (0xffff0000)
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#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
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/*-----------------------------------------------------------------------
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* DER - Timer Decrementer
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*-----------------------------------------------------------------------
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* Initialise to zero
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*/
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#define CONFIG_SYS_DER 0x00000000
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#endif /* __CONFIG_H */
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