mirror of
https://github.com/AsahiLinux/u-boot
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c05ed00afb
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
1040 lines
27 KiB
C
1040 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2015 Google, Inc
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* Copyright 2014 Rockchip Inc.
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* Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <asm/io.h>
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#include <i2c.h>
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#include <media_bus_format.h>
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#include <linux/delay.h>
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#include "dw_hdmi.h"
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struct tmds_n_cts {
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u32 tmds;
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u32 cts;
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u32 n;
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};
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static const struct tmds_n_cts n_cts_table[] = {
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{
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.tmds = 25175000, .n = 6144, .cts = 25175,
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}, {
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.tmds = 25200000, .n = 6144, .cts = 25200,
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}, {
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.tmds = 27000000, .n = 6144, .cts = 27000,
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}, {
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.tmds = 27027000, .n = 6144, .cts = 27027,
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}, {
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.tmds = 40000000, .n = 6144, .cts = 40000,
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}, {
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.tmds = 54000000, .n = 6144, .cts = 54000,
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}, {
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.tmds = 54054000, .n = 6144, .cts = 54054,
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}, {
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.tmds = 65000000, .n = 6144, .cts = 65000,
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}, {
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.tmds = 74176000, .n = 11648, .cts = 140625,
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}, {
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.tmds = 74250000, .n = 6144, .cts = 74250,
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}, {
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.tmds = 83500000, .n = 6144, .cts = 83500,
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}, {
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.tmds = 106500000, .n = 6144, .cts = 106500,
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}, {
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.tmds = 108000000, .n = 6144, .cts = 108000,
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}, {
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.tmds = 148352000, .n = 5824, .cts = 140625,
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}, {
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.tmds = 148500000, .n = 6144, .cts = 148500,
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}, {
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.tmds = 297000000, .n = 5120, .cts = 247500,
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}
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};
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static const u16 csc_coeff_default[3][4] = {
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{ 0x2000, 0x0000, 0x0000, 0x0000 },
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{ 0x0000, 0x2000, 0x0000, 0x0000 },
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{ 0x0000, 0x0000, 0x2000, 0x0000 }
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};
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static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
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{ 0x2591, 0x1322, 0x074b, 0x0000 },
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{ 0x6535, 0x2000, 0x7acc, 0x0200 },
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{ 0x6acd, 0x7534, 0x2000, 0x0200 }
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};
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static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
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{ 0x2000, 0x6926, 0x74fd, 0x010e },
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{ 0x2000, 0x2cdd, 0x0000, 0x7e9a },
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{ 0x2000, 0x0000, 0x38b4, 0x7e3b }
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};
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static void dw_hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset)
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{
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switch (hdmi->reg_io_width) {
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case 1:
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writeb(val, hdmi->ioaddr + offset);
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break;
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case 4:
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writel(val, hdmi->ioaddr + (offset << 2));
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break;
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default:
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debug("reg_io_width has unsupported width!\n");
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break;
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}
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}
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static u8 dw_hdmi_read(struct dw_hdmi *hdmi, int offset)
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{
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switch (hdmi->reg_io_width) {
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case 1:
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return readb(hdmi->ioaddr + offset);
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case 4:
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return readl(hdmi->ioaddr + (offset << 2));
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default:
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debug("reg_io_width has unsupported width!\n");
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break;
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}
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return 0;
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}
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static u8 (*hdmi_read)(struct dw_hdmi *hdmi, int offset) = dw_hdmi_read;
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static void (*hdmi_write)(struct dw_hdmi *hdmi, u8 val, int offset) =
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dw_hdmi_write;
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static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data)
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{
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u8 val = hdmi_read(hdmi, reg) & ~mask;
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val |= data & mask;
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hdmi_write(hdmi, val, reg);
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}
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static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts)
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{
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uint cts3;
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uint n3;
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/* first set ncts_atomic_write (if present) */
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n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE;
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hdmi_write(hdmi, n3, HDMI_AUD_N3);
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/* set cts_manual (if present) */
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cts3 = HDMI_AUD_CTS3_CTS_MANUAL;
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cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET;
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cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK;
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/* write cts values; cts3 must be written first */
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hdmi_write(hdmi, cts3, HDMI_AUD_CTS3);
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hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
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hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1);
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/* write n values; n1 must be written last */
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n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK;
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hdmi_write(hdmi, n3, HDMI_AUD_N3);
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hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
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hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3);
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hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS);
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}
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static int hdmi_lookup_n_cts(u32 pixel_clk)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(n_cts_table); i++)
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if (pixel_clk <= n_cts_table[i].tmds)
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break;
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if (i >= ARRAY_SIZE(n_cts_table))
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return -1;
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return i;
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}
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static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk)
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{
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u32 clk_n, clk_cts;
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int index;
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index = hdmi_lookup_n_cts(pixel_clk);
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if (index == -1) {
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debug("audio not supported for pixel clk %d\n", pixel_clk);
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return;
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}
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clk_n = n_cts_table[index].n;
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clk_cts = n_cts_table[index].cts;
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hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts);
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}
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/*
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* this submodule is responsible for the video data synchronization.
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* for example, for rgb 4:4:4 input, the data map is defined as
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* pin{47~40} <==> r[7:0]
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* pin{31~24} <==> g[7:0]
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* pin{15~8} <==> b[7:0]
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*/
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static void hdmi_video_sample(struct dw_hdmi *hdmi)
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{
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u32 color_format;
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uint val;
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switch (hdmi->hdmi_data.enc_in_bus_format) {
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case MEDIA_BUS_FMT_RGB888_1X24:
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color_format = 0x01;
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break;
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case MEDIA_BUS_FMT_RGB101010_1X30:
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color_format = 0x03;
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break;
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case MEDIA_BUS_FMT_RGB121212_1X36:
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color_format = 0x05;
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break;
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case MEDIA_BUS_FMT_RGB161616_1X48:
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color_format = 0x07;
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break;
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case MEDIA_BUS_FMT_YUV8_1X24:
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case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
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color_format = 0x09;
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break;
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case MEDIA_BUS_FMT_YUV10_1X30:
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case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
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color_format = 0x0B;
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break;
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case MEDIA_BUS_FMT_YUV12_1X36:
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case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
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color_format = 0x0D;
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break;
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case MEDIA_BUS_FMT_YUV16_1X48:
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case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
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color_format = 0x0F;
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break;
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case MEDIA_BUS_FMT_UYVY8_1X16:
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color_format = 0x16;
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break;
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case MEDIA_BUS_FMT_UYVY10_1X20:
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color_format = 0x14;
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break;
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case MEDIA_BUS_FMT_UYVY12_1X24:
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color_format = 0x12;
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break;
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default:
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color_format = 0x01;
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break;
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}
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val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
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((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
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HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
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hdmi_write(hdmi, val, HDMI_TX_INVID0);
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/* enable tx stuffing: when de is inactive, fix the output data to 0 */
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val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
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HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
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HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
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hdmi_write(hdmi, val, HDMI_TX_INSTUFFING);
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hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0);
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hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1);
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hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0);
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hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1);
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hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0);
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hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1);
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}
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static void hdmi_video_packetize(struct dw_hdmi *hdmi)
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{
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u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
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u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT;
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u32 color_depth = 0;
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uint val, vp_conf;
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/* set the packetizer registers */
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val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
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HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
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((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
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HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
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hdmi_write(hdmi, val, HDMI_VP_PR_CD);
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hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK,
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HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE);
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/* data from pixel repeater block */
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vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
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HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
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hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK |
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HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf);
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hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
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1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET);
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hdmi_write(hdmi, remap_size, HDMI_VP_REMAP);
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vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
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HDMI_VP_CONF_PP_EN_DISABLE |
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HDMI_VP_CONF_YCC422_EN_DISABLE;
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hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK |
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HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK,
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vp_conf);
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hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK |
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HDMI_VP_STUFF_YCC422_STUFFING_MASK,
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HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
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HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE);
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hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
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output_select);
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}
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static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit)
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{
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hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK,
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bit << HDMI_PHY_TST0_TSTCLR_OFFSET);
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}
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static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec)
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{
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ulong start;
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u32 val;
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start = get_timer(0);
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do {
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val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0);
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if (val & 0x3) {
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hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
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return 0;
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}
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udelay(100);
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} while (get_timer(start) < msec);
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return 1;
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}
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static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr)
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{
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hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0);
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hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
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hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR);
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hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR);
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hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
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HDMI_PHY_I2CM_OPERATION_ADDR);
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hdmi_phy_wait_i2c_done(hdmi, 1000);
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}
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static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK,
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enable << HDMI_PHY_CONF0_PDZ_OFFSET);
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}
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static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK,
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enable << HDMI_PHY_CONF0_ENTMDS_OFFSET);
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}
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static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK,
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enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET);
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}
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static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK,
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enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET);
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}
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static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0,
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HDMI_PHY_CONF0_GEN2_TXPWRON_MASK,
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enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET);
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}
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static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0,
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HDMI_PHY_CONF0_SELDATAENPOL_MASK,
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enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET);
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}
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static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi,
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uint enable)
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{
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hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK,
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enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET);
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}
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static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock)
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{
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ulong start;
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uint i, val;
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if (!hdmi->mpll_cfg || !hdmi->phy_cfg)
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return -1;
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/* gen2 tx power off */
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hdmi_phy_gen2_txpwron(hdmi, 0);
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/* gen2 pddq */
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hdmi_phy_gen2_pddq(hdmi, 1);
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/* phy reset */
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hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
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hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
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hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
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hdmi_phy_test_clear(hdmi, 1);
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hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
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HDMI_PHY_I2CM_SLAVE_ADDR);
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hdmi_phy_test_clear(hdmi, 0);
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/* pll/mpll cfg - always match on final entry */
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for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++)
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if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock)
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break;
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hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG);
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hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL);
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hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL);
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hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL);
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hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE);
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for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++)
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if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock)
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break;
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/*
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* resistance term 133ohm cfg
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* preemp cgf 0.00
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* tx/ck lvl 10
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*/
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hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM);
|
|
hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL);
|
|
hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL);
|
|
|
|
/* remove clk term */
|
|
hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL);
|
|
|
|
hdmi_phy_enable_power(hdmi, 1);
|
|
|
|
/* toggle tmds enable */
|
|
hdmi_phy_enable_tmds(hdmi, 0);
|
|
hdmi_phy_enable_tmds(hdmi, 1);
|
|
|
|
/* gen2 tx power on */
|
|
hdmi_phy_gen2_txpwron(hdmi, 1);
|
|
hdmi_phy_gen2_pddq(hdmi, 0);
|
|
|
|
hdmi_phy_enable_spare(hdmi, 1);
|
|
|
|
/* wait for phy pll lock */
|
|
start = get_timer(0);
|
|
do {
|
|
val = hdmi_read(hdmi, HDMI_PHY_STAT0);
|
|
if (!(val & HDMI_PHY_TX_PHY_LOCK))
|
|
return 0;
|
|
|
|
udelay(100);
|
|
} while (get_timer(start) < 5);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static void hdmi_av_composer(struct dw_hdmi *hdmi,
|
|
const struct display_timing *edid)
|
|
{
|
|
bool mdataenablepolarity = true;
|
|
uint inv_val;
|
|
uint hbl;
|
|
uint vbl;
|
|
|
|
hbl = edid->hback_porch.typ + edid->hfront_porch.typ +
|
|
edid->hsync_len.typ;
|
|
vbl = edid->vback_porch.typ + edid->vfront_porch.typ +
|
|
edid->vsync_len.typ;
|
|
|
|
/* set up hdmi_fc_invidconf */
|
|
inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
|
|
|
|
inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ?
|
|
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
|
|
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
|
|
|
|
inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ?
|
|
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
|
|
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
|
|
|
|
inv_val |= (mdataenablepolarity ?
|
|
HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
|
|
HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
|
|
|
|
inv_val |= (edid->hdmi_monitor ?
|
|
HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
|
|
HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE);
|
|
|
|
inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
|
|
|
|
inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
|
|
|
|
hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF);
|
|
|
|
/* set up horizontal active pixel width */
|
|
hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1);
|
|
hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0);
|
|
|
|
/* set up vertical active lines */
|
|
hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1);
|
|
hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0);
|
|
|
|
/* set up horizontal blanking pixel region width */
|
|
hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1);
|
|
hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0);
|
|
|
|
/* set up vertical blanking pixel region width */
|
|
hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK);
|
|
|
|
/* set up hsync active edge delay width (in pixel clks) */
|
|
hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1);
|
|
hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0);
|
|
|
|
/* set up vsync active edge delay (in lines) */
|
|
hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY);
|
|
|
|
/* set up hsync active pulse width (in pixel clks) */
|
|
hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1);
|
|
hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0);
|
|
|
|
/* set up vsync active edge delay (in lines) */
|
|
hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH);
|
|
}
|
|
|
|
static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
|
|
{
|
|
switch (bus_format) {
|
|
case MEDIA_BUS_FMT_RGB888_1X24:
|
|
case MEDIA_BUS_FMT_RGB101010_1X30:
|
|
case MEDIA_BUS_FMT_RGB121212_1X36:
|
|
case MEDIA_BUS_FMT_RGB161616_1X48:
|
|
return true;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
|
|
{
|
|
switch (bus_format) {
|
|
case MEDIA_BUS_FMT_YUV8_1X24:
|
|
case MEDIA_BUS_FMT_YUV10_1X30:
|
|
case MEDIA_BUS_FMT_YUV12_1X36:
|
|
case MEDIA_BUS_FMT_YUV16_1X48:
|
|
return true;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
|
|
{
|
|
switch (bus_format) {
|
|
case MEDIA_BUS_FMT_UYVY8_1X16:
|
|
case MEDIA_BUS_FMT_UYVY10_1X20:
|
|
case MEDIA_BUS_FMT_UYVY12_1X24:
|
|
return true;
|
|
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static int is_color_space_interpolation(struct dw_hdmi *hdmi)
|
|
{
|
|
if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
|
|
return 0;
|
|
|
|
if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
|
|
hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int is_color_space_decimation(struct dw_hdmi *hdmi)
|
|
{
|
|
if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
|
|
return 0;
|
|
|
|
if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
|
|
hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
|
|
{
|
|
switch (bus_format) {
|
|
case MEDIA_BUS_FMT_RGB888_1X24:
|
|
case MEDIA_BUS_FMT_YUV8_1X24:
|
|
case MEDIA_BUS_FMT_UYVY8_1X16:
|
|
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
|
|
return 8;
|
|
|
|
case MEDIA_BUS_FMT_RGB101010_1X30:
|
|
case MEDIA_BUS_FMT_YUV10_1X30:
|
|
case MEDIA_BUS_FMT_UYVY10_1X20:
|
|
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
|
|
return 10;
|
|
|
|
case MEDIA_BUS_FMT_RGB121212_1X36:
|
|
case MEDIA_BUS_FMT_YUV12_1X36:
|
|
case MEDIA_BUS_FMT_UYVY12_1X24:
|
|
case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
|
|
return 12;
|
|
|
|
case MEDIA_BUS_FMT_RGB161616_1X48:
|
|
case MEDIA_BUS_FMT_YUV16_1X48:
|
|
case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
|
|
return 16;
|
|
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
static int is_color_space_conversion(struct dw_hdmi *hdmi)
|
|
{
|
|
return hdmi->hdmi_data.enc_in_bus_format !=
|
|
hdmi->hdmi_data.enc_out_bus_format;
|
|
}
|
|
|
|
static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
|
|
{
|
|
const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
|
|
unsigned int i;
|
|
u32 csc_scale = 1;
|
|
|
|
if (is_color_space_conversion(hdmi)) {
|
|
if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
|
|
csc_coeff = &csc_coeff_rgb_out_eitu601;
|
|
} else if (hdmi_bus_fmt_is_rgb(
|
|
hdmi->hdmi_data.enc_in_bus_format)) {
|
|
csc_coeff = &csc_coeff_rgb_in_eitu601;
|
|
csc_scale = 0;
|
|
}
|
|
}
|
|
|
|
/* The CSC registers are sequential, alternating MSB then LSB */
|
|
for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
|
|
u16 coeff_a = (*csc_coeff)[0][i];
|
|
u16 coeff_b = (*csc_coeff)[1][i];
|
|
u16 coeff_c = (*csc_coeff)[2][i];
|
|
|
|
hdmi_write(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
|
|
hdmi_write(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
|
|
hdmi_write(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
|
|
hdmi_write(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
|
|
hdmi_write(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
|
|
hdmi_write(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
|
|
}
|
|
|
|
hdmi_mod(hdmi, HDMI_CSC_SCALE, HDMI_CSC_SCALE_CSCSCALE_MASK, csc_scale);
|
|
}
|
|
|
|
static void hdmi_video_csc(struct dw_hdmi *hdmi)
|
|
{
|
|
int color_depth = 0;
|
|
int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
|
|
int decimation = 0;
|
|
|
|
/* YCC422 interpolation to 444 mode */
|
|
if (is_color_space_interpolation(hdmi))
|
|
interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
|
|
else if (is_color_space_decimation(hdmi))
|
|
decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
|
|
|
|
switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
|
|
case 8:
|
|
color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
|
|
break;
|
|
case 10:
|
|
color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
|
|
break;
|
|
case 12:
|
|
color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
|
|
break;
|
|
case 16:
|
|
color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
|
|
break;
|
|
|
|
default:
|
|
return;
|
|
}
|
|
|
|
/* Configure the CSC registers */
|
|
hdmi_write(hdmi, interpolation | decimation, HDMI_CSC_CFG);
|
|
|
|
hdmi_mod(hdmi, HDMI_CSC_SCALE, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
|
|
color_depth);
|
|
|
|
dw_hdmi_update_csc_coeffs(hdmi);
|
|
}
|
|
|
|
/* hdmi initialization step b.4 */
|
|
static void hdmi_enable_video_path(struct dw_hdmi *hdmi, bool audio)
|
|
{
|
|
uint clkdis;
|
|
|
|
/* control period minimum duration */
|
|
hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR);
|
|
hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR);
|
|
hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC);
|
|
|
|
/* set to fill tmds data channels */
|
|
hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM);
|
|
hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM);
|
|
hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM);
|
|
|
|
hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
|
|
HDMI_MC_FLOWCTRL);
|
|
|
|
/* enable pixel clock and tmds data path */
|
|
clkdis = 0x7f;
|
|
clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
|
|
hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
|
|
|
|
clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
|
|
hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
|
|
|
|
/* Enable csc path */
|
|
if (is_color_space_conversion(hdmi)) {
|
|
clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
|
|
hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
|
|
}
|
|
|
|
/* Enable color space conversion if needed */
|
|
if (is_color_space_conversion(hdmi))
|
|
hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
|
|
HDMI_MC_FLOWCTRL);
|
|
else
|
|
hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
|
|
HDMI_MC_FLOWCTRL);
|
|
|
|
if (audio) {
|
|
clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
|
|
hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS);
|
|
}
|
|
}
|
|
|
|
/* workaround to clear the overflow condition */
|
|
static void hdmi_clear_overflow(struct dw_hdmi *hdmi)
|
|
{
|
|
uint val, count;
|
|
|
|
/* tmds software reset */
|
|
hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
|
|
|
|
val = hdmi_read(hdmi, HDMI_FC_INVIDCONF);
|
|
|
|
for (count = 0; count < 4; count++)
|
|
hdmi_write(hdmi, val, HDMI_FC_INVIDCONF);
|
|
}
|
|
|
|
static void hdmi_audio_set_format(struct dw_hdmi *hdmi)
|
|
{
|
|
hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0,
|
|
HDMI_AUD_CONF0);
|
|
|
|
|
|
hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE |
|
|
HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1);
|
|
|
|
hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2);
|
|
}
|
|
|
|
static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi)
|
|
{
|
|
hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ);
|
|
hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0);
|
|
|
|
hdmi_write(hdmi, 0x00, HDMI_AUD_INT);
|
|
hdmi_write(hdmi, 0x00, HDMI_AUD_INT1);
|
|
}
|
|
|
|
static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi)
|
|
{
|
|
uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD;
|
|
|
|
return !!val;
|
|
}
|
|
|
|
static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
|
|
{
|
|
u32 val;
|
|
ulong start;
|
|
|
|
start = get_timer(0);
|
|
do {
|
|
val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0);
|
|
if (val & 0x2) {
|
|
hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0);
|
|
return 0;
|
|
}
|
|
|
|
udelay(100);
|
|
} while (get_timer(start) < msec);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void hdmi_ddc_reset(struct dw_hdmi *hdmi)
|
|
{
|
|
hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0);
|
|
}
|
|
|
|
static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff)
|
|
{
|
|
int shift = (block % 2) * 0x80;
|
|
int edid_read_err = 0;
|
|
u32 trytime = 5;
|
|
u32 n;
|
|
|
|
if (CONFIG_IS_ENABLED(DM_I2C) && hdmi->ddc_bus) {
|
|
struct udevice *chip;
|
|
|
|
edid_read_err = i2c_get_chip(hdmi->ddc_bus,
|
|
HDMI_I2CM_SLAVE_DDC_ADDR,
|
|
1, &chip);
|
|
if (edid_read_err)
|
|
return edid_read_err;
|
|
|
|
return dm_i2c_read(chip, shift, buff, HDMI_EDID_BLOCK_SIZE);
|
|
}
|
|
|
|
/* set ddc i2c clk which devided from ddc_clk to 100khz */
|
|
hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
|
|
hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
|
|
hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE,
|
|
HDMI_I2CM_DIV_STD_MODE);
|
|
|
|
hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE);
|
|
hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR);
|
|
hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR);
|
|
|
|
while (trytime--) {
|
|
edid_read_err = 0;
|
|
|
|
for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) {
|
|
hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS);
|
|
|
|
if (block == 0)
|
|
hdmi_write(hdmi, HDMI_I2CM_OP_RD8,
|
|
HDMI_I2CM_OPERATION);
|
|
else
|
|
hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT,
|
|
HDMI_I2CM_OPERATION);
|
|
|
|
if (hdmi_ddc_wait_i2c_done(hdmi, 10)) {
|
|
hdmi_ddc_reset(hdmi);
|
|
edid_read_err = 1;
|
|
break;
|
|
}
|
|
|
|
buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI);
|
|
}
|
|
|
|
if (!edid_read_err)
|
|
break;
|
|
}
|
|
|
|
return edid_read_err;
|
|
}
|
|
|
|
static const u8 pre_buf[] = {
|
|
0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
|
|
0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00,
|
|
0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78,
|
|
0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27,
|
|
0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f,
|
|
0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
|
|
0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a,
|
|
0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
|
|
0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
|
|
0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c,
|
|
0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37,
|
|
0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32,
|
|
0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20,
|
|
0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
|
|
0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53,
|
|
0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0,
|
|
0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03,
|
|
0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
|
|
0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07,
|
|
0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
|
|
0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0,
|
|
0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e,
|
|
0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72,
|
|
0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
|
|
0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d,
|
|
0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
|
|
0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e,
|
|
0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
|
|
0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00,
|
|
0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9,
|
|
};
|
|
|
|
int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
|
|
{
|
|
int i, ret;
|
|
|
|
/* hdmi phy spec says to do the phy initialization sequence twice */
|
|
for (i = 0; i < 2; i++) {
|
|
hdmi_phy_sel_data_en_pol(hdmi, 1);
|
|
hdmi_phy_sel_interface_control(hdmi, 0);
|
|
hdmi_phy_enable_tmds(hdmi, 0);
|
|
hdmi_phy_enable_power(hdmi, 0);
|
|
|
|
ret = hdmi_phy_configure(hdmi, mpixelclock);
|
|
if (ret) {
|
|
debug("hdmi phy config failure %d\n", ret);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi)
|
|
{
|
|
ulong start;
|
|
|
|
start = get_timer(0);
|
|
do {
|
|
if (hdmi_get_plug_in_status(hdmi))
|
|
return 0;
|
|
udelay(100);
|
|
} while (get_timer(start) < 300);
|
|
|
|
return -1;
|
|
}
|
|
|
|
void dw_hdmi_phy_init(struct dw_hdmi *hdmi)
|
|
{
|
|
/* enable phy i2cm done irq */
|
|
hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
|
|
HDMI_PHY_I2CM_INT_ADDR);
|
|
|
|
/* enable phy i2cm nack & arbitration error irq */
|
|
hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
|
|
HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
|
|
HDMI_PHY_I2CM_CTLINT_ADDR);
|
|
|
|
/* enable cable hot plug irq */
|
|
hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
|
|
|
|
/* clear hotplug interrupts */
|
|
hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
|
|
}
|
|
|
|
int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size)
|
|
{
|
|
u32 edid_size = HDMI_EDID_BLOCK_SIZE;
|
|
int ret;
|
|
|
|
if (0) {
|
|
edid_size = sizeof(pre_buf);
|
|
memcpy(buf, pre_buf, edid_size);
|
|
} else {
|
|
ret = hdmi_read_edid(hdmi, 0, buf);
|
|
if (ret) {
|
|
debug("failed to read edid.\n");
|
|
return -1;
|
|
}
|
|
|
|
if (buf[0x7e] != 0) {
|
|
hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE);
|
|
edid_size += HDMI_EDID_BLOCK_SIZE;
|
|
}
|
|
}
|
|
|
|
return edid_size;
|
|
}
|
|
|
|
int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
|
|
{
|
|
int ret;
|
|
|
|
debug("%s, mode info : clock %d hdis %d vdis %d\n",
|
|
edid->hdmi_monitor ? "hdmi" : "dvi",
|
|
edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ);
|
|
|
|
hdmi_av_composer(hdmi, edid);
|
|
|
|
ret = hdmi->phy_set(hdmi, edid->pixelclock.typ);
|
|
if (ret)
|
|
return ret;
|
|
|
|
hdmi_enable_video_path(hdmi, edid->hdmi_monitor);
|
|
|
|
if (edid->hdmi_monitor) {
|
|
hdmi_audio_fifo_reset(hdmi);
|
|
hdmi_audio_set_format(hdmi);
|
|
hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ);
|
|
}
|
|
|
|
hdmi_video_packetize(hdmi);
|
|
hdmi_video_csc(hdmi);
|
|
hdmi_video_sample(hdmi);
|
|
|
|
hdmi_clear_overflow(hdmi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void dw_hdmi_init(struct dw_hdmi *hdmi)
|
|
{
|
|
uint ih_mute;
|
|
|
|
/*
|
|
* boot up defaults are:
|
|
* hdmi_ih_mute = 0x03 (disabled)
|
|
* hdmi_ih_mute_* = 0x00 (enabled)
|
|
*
|
|
* disable top level interrupt bits in hdmi block
|
|
*/
|
|
ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/
|
|
HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
|
|
HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
|
|
|
|
if (hdmi->write_reg)
|
|
hdmi_write = hdmi->write_reg;
|
|
|
|
if (hdmi->read_reg)
|
|
hdmi_read = hdmi->read_reg;
|
|
|
|
hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE);
|
|
|
|
/* enable i2c master done irq */
|
|
hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT);
|
|
|
|
/* enable i2c client nack % arbitration error irq */
|
|
hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT);
|
|
}
|