mirror of
https://github.com/AsahiLinux/u-boot
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e6e505b93c
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while most of it is just generic code that could as well be used on an AArch64 SoC. Move all files that are not really tied to armv7 into a new mach-sunxi directory. Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
71 lines
1.6 KiB
C
71 lines
1.6 KiB
C
/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
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{
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u32 index = GPIO_CFG_INDEX(bank_offset);
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u32 offset = GPIO_CFG_OFFSET(bank_offset);
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clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
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}
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void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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sunxi_gpio_set_cfgbank(pio, pin, val);
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}
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int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
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{
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u32 index = GPIO_CFG_INDEX(bank_offset);
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u32 offset = GPIO_CFG_OFFSET(bank_offset);
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u32 cfg;
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cfg = readl(&pio->cfg[0] + index);
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cfg >>= offset;
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return cfg & 0xf;
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}
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int sunxi_gpio_get_cfgpin(u32 pin)
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{
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u32 bank = GPIO_BANK(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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return sunxi_gpio_get_cfgbank(pio, pin);
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}
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int sunxi_gpio_set_drv(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_DRV_INDEX(pin);
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u32 offset = GPIO_DRV_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
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return 0;
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}
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int sunxi_gpio_set_pull(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_PULL_INDEX(pin);
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u32 offset = GPIO_PULL_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
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return 0;
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}
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