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https://github.com/AsahiLinux/u-boot
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35e29e89a3
Enabling and disabling PCIe ports is done via address space of system controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register for enabling and disabling some or more PCIe ports. Correct mapping needs to be set in particular DTS files. DT API for mvebu-reset is prepared for implementing resets also for other HW blocks, but currently only PCIe is implemented via index 0. Currently this driver is not used as PCIe ports are automatically enabled by SerDes code executed by U-Boot SPL. But this will change in followup patches. Signed-off-by: Pali Rohár <pali@kernel.org>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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// (C) 2021 Pali Rohár <pali@kernel.org>
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#include <common.h>
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#include <dm.h>
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#include <reset-uclass.h>
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#include <asm/io.h>
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#define MVEBU_SOC_CONTROL_1_REG 0x4
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#define MVEBU_PCIE_ID 0
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struct mvebu_reset_data {
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void *base;
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};
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static int mvebu_reset_of_xlate(struct reset_ctl *rst,
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struct ofnode_phandle_args *args)
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{
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if (args->args_count < 2)
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return -EINVAL;
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rst->id = args->args[0];
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rst->data = args->args[1];
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/* Currently only PCIe is implemented */
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if (rst->id != MVEBU_PCIE_ID)
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return -EINVAL;
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/* Four PCIe enable bits are shared across more PCIe links */
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if (!(rst->data >= 0 && rst->data <= 3))
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return -EINVAL;
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return 0;
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}
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static int mvebu_reset_request(struct reset_ctl *rst)
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{
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return 0;
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}
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static int mvebu_reset_free(struct reset_ctl *rst)
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{
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return 0;
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}
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static int mvebu_reset_assert(struct reset_ctl *rst)
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{
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struct mvebu_reset_data *data = dev_get_priv(rst->dev);
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clrbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data));
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return 0;
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}
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static int mvebu_reset_deassert(struct reset_ctl *rst)
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{
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struct mvebu_reset_data *data = dev_get_priv(rst->dev);
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setbits_32(data->base + MVEBU_SOC_CONTROL_1_REG, BIT(rst->data));
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return 0;
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}
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static int mvebu_reset_status(struct reset_ctl *rst)
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{
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struct mvebu_reset_data *data = dev_get_priv(rst->dev);
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return !(readl(data->base + MVEBU_SOC_CONTROL_1_REG) & BIT(rst->data));
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}
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static int mvebu_reset_of_to_plat(struct udevice *dev)
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{
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struct mvebu_reset_data *data = dev_get_priv(dev);
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data->base = (void *)dev_read_addr(dev);
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if ((fdt_addr_t)data->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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static const struct udevice_id mvebu_reset_of_match[] = {
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{ .compatible = "marvell,armada-370-xp-system-controller" },
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{ .compatible = "marvell,armada-375-system-controller" },
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{ .compatible = "marvell,armada-380-system-controller" },
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{ .compatible = "marvell,armada-390-system-controller" },
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{ },
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};
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static struct reset_ops mvebu_reset_ops = {
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.of_xlate = mvebu_reset_of_xlate,
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.request = mvebu_reset_request,
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.rfree = mvebu_reset_free,
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.rst_assert = mvebu_reset_assert,
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.rst_deassert = mvebu_reset_deassert,
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.rst_status = mvebu_reset_status,
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};
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U_BOOT_DRIVER(mvebu_reset) = {
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.name = "mvebu-reset",
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.id = UCLASS_RESET,
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.of_match = mvebu_reset_of_match,
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.of_to_plat = mvebu_reset_of_to_plat,
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.priv_auto = sizeof(struct mvebu_reset_data),
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.ops = &mvebu_reset_ops,
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};
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