u-boot/arch/arm/mach-keystone/init.c
Nishanth Menon 2283284b05 ARM: keystone2: Add missing privilege ID settings
Add missing Privilege ID settings for KS2 SoCs.

Based on:
K2H/K: Table 6-7. Privilege ID Settings from SPRS866E (Nov 2013)
  http://www.ti.com/lit/ds/symlink/66ak2h14.pdf (page 99)
K2L: Table 7-7. Privilege ID Settings from SPRS930 (April 2015)
  http://www.ti.com/lit/ds/symlink/66ak2l06.pdf (page 71)
K2E: Table 7-7. Privilege ID Settings from SPRS865D (Mar 2015)
  http://www.ti.com/lit/ds/symlink/66ak2e05.pdf (page 75)
K2G: Table 3-16. PrivIDs from SPRUHY8 (Jan 2016)
  http://www.ti.com/lit/ug/spruhy8/spruhy8.pdf (page 238)

Overall mapping:
-------+-----------+-----------+-----------+---------
PrivID | KS2H/K    | K2L       | K2E       | K2G
-------+-----------+-----------+-----------+---------
0      | C66x 0    | C66x 0    | C66x 0    | C66x 0
1      | C66x 1    | C66x 1    | Reserved  | ARM
2      | C66x 2    | C66x 2    | Reserved  | ICSS0
3      | C66x 3    | C66x 3    | Reserved  | ICSS1
4      | C66x 4    | Reserved  | Reserved  | NETCP
5      | C66x 5    | Reserved  | Reserved  | CPIE
6      | C66x 6    | Reserved  | Reserved  | USB
7      | C66x 7    | Reserved  | Reserved  | Reserved
8      | ARM       | ARM       | ARM       | MLB
9      | NetCP     | NetCP     | NetCP     | PMMC
10     | QM_PDSP   | QM_PDSP   | QM_PDSP   | DSS
11     | PCIe_0    | PCIe_0    | PCIe_0    | MMC
12     | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP | DEBUG/DAP
13     | Reserved  | Reserved  | PCIe_1    | Reserved
14     | HyperLink | PCIe_1    | HyperLink | Reserved
15     | Reserved  | Reserved  | TSIP      | Reserved
-------+-----------+-----------+-----------+---------

NOTE: Few of these might have default configurations, however,
since most are software configurable, it is better to explicitly
configure the system to have a known default state.

Without programming these, we end up seeing lack of coherency on certain
peripherals resulting in inexplicable failures (such as USB peripheral's
DMA data not appearing on ARM etc and weird workarounds being done by
drivers including cache flushes which tend to have system wide
performance impact).

By marking these segments as shared, we also ensure SoC wide coherency
is enabled.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-04-01 17:17:40 -04:00

249 lines
5.8 KiB
C

/*
* Keystone2: Architecture initialization
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/psc_defs.h>
#define MAX_PCI_PORTS 2
enum pci_mode {
ENDPOINT,
LEGACY_ENDPOINT,
ROOTCOMPLEX,
};
#define DEVCFG_MODE_MASK (BIT(2) | BIT(1))
#define DEVCFG_MODE_SHIFT 1
void chip_configuration_unlock(void)
{
__raw_writel(KS2_KICK0_MAGIC, KS2_KICK0);
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
#ifdef CONFIG_SOC_K2L
void osr_init(void)
{
u32 i;
u32 j;
u32 val;
u32 base = KS2_OSR_CFG_BASE;
u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
/* Enable the OSR clock domain */
psc_enable_module(KS2_LPSC_OSR);
/* Disable OSR ECC check for all the ram banks */
for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
val = i | KS2_OSR_ECC_VEC_TRIG_RD |
(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
writel(val , base + KS2_OSR_ECC_VEC);
/**
* wait till read is done.
* Print should be added after earlyprintk support is added.
*/
for (j = 0; j < 10000; j++) {
val = readl(base + KS2_OSR_ECC_VEC);
if (val & KS2_OSR_ECC_VEC_RD_DONE)
break;
}
ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
KS2_OSR_ECC_CTRL_CHK;
writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
}
/* Reset OSR memory to all zeros */
for (i = 0; i < KS2_OSR_SIZE; i += 4)
writel(0, KS2_OSR_DATA_BASE + i);
/* Enable OSR ECC check for all the ram banks */
for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
writel(ecc_ctrl[i] |
KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
}
#endif
/* Function to set up PCIe mode */
static void config_pcie_mode(int pcie_port, enum pci_mode mode)
{
u32 val = __raw_readl(KS2_DEVCFG);
if (pcie_port >= MAX_PCI_PORTS)
return;
/**
* each pci port has two bits for mode and it starts at
* bit 1. So use port number to get the right bit position.
*/
pcie_port <<= 1;
val &= ~(DEVCFG_MODE_MASK << pcie_port);
val |= ((mode << DEVCFG_MODE_SHIFT) << pcie_port);
__raw_writel(val, KS2_DEVCFG);
}
static void msmc_k2hkle_common_setup(void)
{
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM);
msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP);
#ifdef KS2_MSMC_SEGMENT_QM_PDSP
msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP);
#endif
msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0);
msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
}
static void msmc_k2hk_setup(void)
{
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_4);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_5);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_6);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_7);
msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
}
static inline void msmc_k2l_setup(void)
{
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_1);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_2);
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_3);
msmc_share_all_segments(K2L_MSMC_SEGMENT_PCIE1);
}
static inline void msmc_k2e_setup(void)
{
msmc_share_all_segments(K2E_MSMC_SEGMENT_PCIE1);
msmc_share_all_segments(K2HKE_MSMC_SEGMENT_HYPERLINK);
msmc_share_all_segments(K2E_MSMC_SEGMENT_TSIP);
}
static void msmc_k2g_setup(void)
{
msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0);
msmc_share_all_segments(K2G_MSMC_SEGMENT_ARM);
msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS0);
msmc_share_all_segments(K2G_MSMC_SEGMENT_ICSS1);
msmc_share_all_segments(K2G_MSMC_SEGMENT_NSS);
msmc_share_all_segments(K2G_MSMC_SEGMENT_PCIE);
msmc_share_all_segments(K2G_MSMC_SEGMENT_USB);
msmc_share_all_segments(K2G_MSMC_SEGMENT_MLB);
msmc_share_all_segments(K2G_MSMC_SEGMENT_PMMC);
msmc_share_all_segments(K2G_MSMC_SEGMENT_DSS);
msmc_share_all_segments(K2G_MSMC_SEGMENT_MMC);
msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG);
}
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
if (cpu_is_k2g()) {
msmc_k2g_setup();
} else {
msmc_k2hkle_common_setup();
if (cpu_is_k2e())
msmc_k2e_setup();
else if (cpu_is_k2l())
msmc_k2l_setup();
else
msmc_k2hk_setup();
}
/* Initialize the PCIe-0 to work as Root Complex */
config_pcie_mode(0, ROOTCOMPLEX);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
/* Initialize the PCIe-1 to work as Root Complex */
config_pcie_mode(1, ROOTCOMPLEX);
#endif
#ifdef CONFIG_SOC_K2L
osr_init();
#endif
/*
* just initialise the COM2 port so that TI specific
* UART register PWREMU_MGMT is initialized. Linux UART
* driver doesn't handle this.
*/
#ifndef CONFIG_DM_SERIAL
NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
#endif
return 0;
}
void reset_cpu(ulong addr)
{
volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
u32 tmp;
tmp = *rstctrl & KS2_RSTCTRL_MASK;
*rstctrl = tmp | KS2_RSTCTRL_KEY;
*rstctrl &= KS2_RSTCTRL_SWRST;
for (;;)
;
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
#endif
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u16 cpu = get_part_number();
u8 rev = cpu_revision();
puts("CPU: ");
switch (cpu) {
case CPU_66AK2Hx:
puts("66AK2Hx SR");
break;
case CPU_66AK2Lx:
puts("66AK2Lx SR");
break;
case CPU_66AK2Ex:
puts("66AK2Ex SR");
break;
case CPU_66AK2Gx:
puts("66AK2Gx SR");
break;
default:
puts("Unknown\n");
}
if (rev == 2)
puts("2.0\n");
else if (rev == 1)
puts("1.1\n");
else if (rev == 0)
puts("1.0\n");
return 0;
}
#endif