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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
141 lines
6.6 KiB
C
141 lines
6.6 KiB
C
/*
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* Freescale DMA Controller
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*
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* Copyright 2006 Freescale Semiconductor, Inc.
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*
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* This software may be used and distributed according to the
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* terms of the GNU Public License, Version 2, incorporated
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* herein by reference.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_FSL_DMA_H_
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#define _ASM_FSL_DMA_H_
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#include <asm/types.h>
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#ifdef CONFIG_MPC83xx
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typedef struct fsl_dma {
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uint mr; /* DMA mode register */
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#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
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#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
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#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
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#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
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#define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
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#define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
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#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
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#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
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#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
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#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
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#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
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#define FSL_DMA_MR_IRQS 0x00080000 /* Interrupt steer */
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#define FSL_DMA_MR_DMSEN 0x00100000 /* Direct mode snooping en */
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#define FSL_DMA_MR_BWC_MASK 0x00e00000 /* Bandwidth/pause ctl */
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#define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */
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uint sr; /* DMA status register */
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#define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */
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#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
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#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
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#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
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uint cdar; /* DMA current descriptor address register */
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char res0[4];
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uint sar; /* DMA source address register */
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char res1[4];
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uint dar; /* DMA destination address register */
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char res2[4];
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uint bcr; /* DMA byte count register */
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uint ndar; /* DMA next descriptor address register */
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uint gsr; /* DMA general status register (DMA3 ONLY!) */
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char res3[84];
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} fsl_dma_t;
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#else
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typedef struct fsl_dma {
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uint mr; /* DMA mode register */
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#define FSL_DMA_MR_CS 0x00000001 /* Channel start */
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#define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
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#define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
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#define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
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#define FSL_DMA_MR_CA 0x00000008 /* Channel abort */
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#define FSL_DMA_MR_CDSM 0x00000010
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#define FSL_DMA_MR_XFE 0x00000020 /* Extended features en */
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#define FSL_DMA_MR_EIE 0x00000040 /* Error interrupt en */
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#define FSL_DMA_MR_EOLSIE 0x00000080 /* End-of-lists interrupt en */
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#define FSL_DMA_MR_EOLNIE 0x00000100 /* End-of-links interrupt en */
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#define FSL_DMA_MR_EOSIE 0x00000200 /* End-of-seg interrupt en */
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#define FSL_DMA_MR_SRW 0x00000400 /* Single register write */
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#define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
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#define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
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#define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
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#define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
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#define FSL_DMA_MR_EMS_EN 0x00040000 /* Ext master start en */
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#define FSL_DMA_MR_EMP_EN 0x00200000 /* Ext master pause en */
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#define FSL_DMA_MR_BWC_MASK 0x0f000000 /* Bandwidth/pause ctl */
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#define FSL_DMA_MR_BWC_DIS 0x0f000000 /* Bandwidth/pause ctl disable */
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uint sr; /* DMA status register */
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#define FSL_DMA_SR_EOLSI 0x00000001 /* End-of-list interrupt */
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#define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
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#define FSL_DMA_SR_CB 0x00000004 /* Channel busy */
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#define FSL_DMA_SR_EOLNI 0x00000008 /* End-of-links interrupt */
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#define FSL_DMA_SR_PE 0x00000010 /* Programming error */
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#define FSL_DMA_SR_CH 0x00000020 /* Channel halted */
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#define FSL_DMA_SR_TE 0x00000080 /* Transfer error */
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char res0[4];
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uint clndar; /* DMA current link descriptor address register */
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uint satr; /* DMA source attributes register */
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#define FSL_DMA_SATR_ESAD_MASK 0x000001ff /* Extended source addr */
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#define FSL_DMA_SATR_SREAD_NO_SNOOP 0x00040000 /* Read, don't snoop */
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#define FSL_DMA_SATR_SREAD_SNOOP 0x00050000 /* Read, snoop */
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#define FSL_DMA_SATR_SREAD_UNLOCK 0x00070000 /* Read, unlock l2 */
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#define FSL_DMA_SATR_STRAN_MASK 0x00f00000 /* Source interface */
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#define FSL_DMA_SATR_SSME 0x01000000 /* Source stride en */
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#define FSL_DMA_SATR_SPCIORDER 0x02000000 /* PCI transaction order */
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#define FSL_DMA_SATR_STFLOWLVL_MASK 0x0c000000 /* RIO flow level */
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#define FSL_DMA_SATR_SBPATRMU 0x20000000 /* Bypass ATMU */
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uint sar; /* DMA source address register */
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uint datr; /* DMA destination attributes register */
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#define FSL_DMA_DATR_EDAD_MASK 0x000001ff /* Extended dest addr */
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#define FSL_DMA_DATR_DWRITE_NO_SNOOP 0x00040000 /* Write, don't snoop */
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#define FSL_DMA_DATR_DWRITE_SNOOP 0x00050000 /* Write, snoop */
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#define FSL_DMA_DATR_DWRITE_ALLOC 0x00060000 /* Write, alloc l2 */
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#define FSL_DMA_DATR_DWRITE_LOCK 0x00070000 /* Write, lock l2 */
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#define FSL_DMA_DATR_DTRAN_MASK 0x00f00000 /* Dest interface */
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#define FSL_DMA_DATR_DSME 0x01000000 /* Dest stride en */
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#define FSL_DMA_DATR_DPCIORDER 0x02000000 /* PCI transaction order */
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#define FSL_DMA_DATR_DTFLOWLVL_MASK 0x0c000000 /* RIO flow level */
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#define FSL_DMA_DATR_DBPATRMU 0x20000000 /* Bypass ATMU */
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uint dar; /* DMA destination address register */
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uint bcr; /* DMA byte count register */
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char res1[4];
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uint nlndar; /* DMA next link descriptor address register */
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char res2[8];
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uint clabdar; /* DMA current List - alternate base descriptor address Register */
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char res3[4];
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uint nlsdar; /* DMA next list descriptor address register */
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uint ssr; /* DMA source stride register */
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uint dsr; /* DMA destination stride register */
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char res4[56];
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} fsl_dma_t;
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#endif /* !CONFIG_MPC83xx */
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#ifdef CONFIG_FSL_DMA
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void dma_init(void);
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int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t n);
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#if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
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void dma_meminit(uint val, uint size);
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#endif
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#endif
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#endif /* _ASM_DMA_H_ */
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