mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
360 lines
8.3 KiB
C
360 lines
8.3 KiB
C
/*
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* genietv/genietv.c
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*
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* The GENIETV is using the following physical memorymap (copied from
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* the FADS configuration):
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*
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* ff020000 -> ff02ffff : pcmcia
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* ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM
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* ff000000 -> ff00ffff : IMAP internal in the cpu
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* 02800000 -> 0287ffff : flash connected to CS0
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* 00000000 -> nnnnnnnn : sdram setup by U-Boot
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*
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* CS pins are connected as follows:
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*
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* CS0 -512Kb boot flash
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* CS1 - SDRAM #1
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* CS2 - SDRAM #2
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* CS3 - Flash #1
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* CS4 - Flash #2
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* CS5 - LON (if present)
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* CS6 - PCMCIA #1
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* CS7 - PCMCIA #2
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*
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* Ports are configured as follows:
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*
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* PA7 - SDRAM banks enable
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#define CFG_PA7 0x0100
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMB RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBEEC00,
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0x1FFDDC47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMB RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FFDDC34, 0xEFEEAC34, 0x1FBD5C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMB RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBEEC00, 0x1FFDDC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMB RAM)
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*/
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0x1F2DFC04, 0xEEAFAC00, 0x01BE4C04, 0x1FFDDC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMB RAM)
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*/
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0x1F0DFC04, 0xEEAFAC00, 0x10AF5C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BEEC04, 0x1FFDDC47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMB RAM)
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*/
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMB RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity
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*/
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int checkboard (void)
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{
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puts ("Board: GenieTV\n");
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return 0;
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}
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#if 0
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static void PrintState (void)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &im->im_memctl;
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printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
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memctl->memc_or0);
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printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
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memctl->memc_or1);
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printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
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memctl->memc_or2);
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}
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#endif
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &im->im_memctl;
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long int size_b0, size_b1, size8;
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/* Enable SDRAM */
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/* Configuring PA7 for general purpouse output pin */
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im->im_ioport.iop_papar &= ~CFG_PA7; /* 0 = general purpouse */
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im->im_ioport.iop_padir |= CFG_PA7; /* 1 = output */
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/* Enable SDRAM - PA7 = 1 */
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im->im_ioport.iop_padat |= CFG_PA7; /* value of PA7 */
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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memctl->memc_mbmr = CFG_MBMR_8COL;
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upmconfig (UPMB, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
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memctl->memc_br1 =
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((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
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memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
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/* perform SDRAM initialization sequence */
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memctl->memc_mar = 0x00000088;
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memctl->memc_mcr = 0x80802105; /* SDRAM bank 0 */
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memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
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/* Execute refresh 8 times */
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memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
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memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */
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memctl->memc_mcr = 0x80804130; /* SDRAM bank 1 - execute twice */
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/* Execute refresh 4 times */
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memctl->memc_mbmr = CFG_MBMR_8COL;
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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#if 0
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PrintState ();
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#endif
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/* printf ("\nChecking bank1..."); */
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size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
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SDRAM_MAX_SIZE);
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size_b0 = size8;
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/* printf ("\nChecking bank2..."); */
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size_b1 =
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dram_size (memctl->memc_mbmr, (long *) SDRAM_BASE2_PRELIM,
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SDRAM_MAX_SIZE);
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/*
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* Final mapping: map bigger bank first
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*/
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memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
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if (size_b1 > 0) {
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/*
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* Position Bank 1 immediately above Bank 0
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*/
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memctl->memc_or2 =
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((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
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(size_b0 & BR_BA_MSK);
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} else {
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/*
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* No bank 1
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*
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* invalidate bank
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*/
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memctl->memc_br2 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
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}
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/* If no memory detected, disable SDRAM */
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if ((size_b0 + size_b1) == 0) {
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printf ("disabling SDRAM!\n");
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/* Disable SDRAM - PA7 = 1 */
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im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */
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}
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/* else */
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/* printf("done! (%08lx)\n", size_b0 + size_b1); */
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#if 0
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PrintState ();
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#endif
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return (size_b0 + size_b1);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mbmr_value, long int *base,
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long int maxsize)
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{
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long size;
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/*memctl->memc_mbmr = mbmr_value; */
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size = get_ram_size (base, maxsize);
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if (size) {
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/* printf("(%08lx)", size); */
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} else {
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printf ("(0)");
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}
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return (size);
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}
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
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#ifdef CFG_PCMCIA_MEM_ADDR
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volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR;
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#endif
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int pcmcia_init (void)
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{
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volatile pcmconf8xx_t *pcmp;
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uint v, slota, slotb;
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/*
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** Enable the PCMCIA for a Flash card.
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*/
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pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
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#if 0
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pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
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pcmp->pcmc_por0 = 0xc00ff05d;
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#endif
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/* Set all slots to zero by default. */
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pcmp->pcmc_pgcra = 0;
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pcmp->pcmc_pgcrb = 0;
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#ifdef PCMCIA_SLOT_A
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pcmp->pcmc_pgcra = 0x40;
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#endif
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#ifdef PCMCIA_SLOT_B
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pcmp->pcmc_pgcrb = 0x40;
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#endif
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/* Check if any PCMCIA card is luged in. */
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slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
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slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
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if (!(slota || slotb)) {
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printf ("No card present\n");
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#ifdef PCMCIA_SLOT_A
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pcmp->pcmc_pgcra = 0;
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#endif
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#ifdef PCMCIA_SLOT_B
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pcmp->pcmc_pgcrb = 0;
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#endif
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return -1;
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} else
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printf ("Unknown card (");
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v = 0;
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switch ((pcmp->pcmc_pipr >> 14) & 3) {
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case 0x00:
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printf ("5V");
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v = 5;
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break;
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case 0x01:
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printf ("5V and 3V");
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v = 3;
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break;
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case 0x03:
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printf ("5V, 3V and x.xV");
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v = 3;
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break;
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}
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switch (v) {
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case 3:
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printf ("; using 3V");
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/* Enable 3 volt Vcc. */
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break;
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default:
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printf ("; unknown voltage");
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return -1;
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}
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printf (")\n");
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/* disable pcmcia reset after a while */
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udelay (20);
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pcmp->pcmc_pgcrb = 0;
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/* If you using a real hd you should give a short
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* spin-up time. */
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#ifdef CONFIG_DISK_SPINUP_TIME
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udelay (CONFIG_DISK_SPINUP_TIME);
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#endif
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return 0;
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}
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#endif /* CFG_CMD_PCMCIA */
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