mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
6b87abe3ac
SH4 and SH4A are compatible. But some instructions are different from these. In Linux kernel, It is treated as a separate CPU, but for now, I think that there is no need to divide especially in the U-Boot. This removes CONFIG_SH4A definition from source code, SH4A is treated as SH4. And this fix white space. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
167 lines
5.1 KiB
C
167 lines
5.1 KiB
C
/*
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* Configuation settings for the Renesas Solutions r0p7734 board
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*
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* Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __R0P7734_H
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#define __R0P7734_H
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#undef DEBUG
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#define CONFIG_CPU_SH7734 1
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#define CONFIG_R0P7734 1
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#define CONFIG_400MHZ_MODE 1
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/* #define CONFIG_533MHZ_MODE 1 */
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttySC3,115200"
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#define CONFIG_VERSION_VARIABLE
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* Ether */
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#define CONFIG_SH_ETHER 1
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#define CONFIG_SH_ETHER_USE_PORT (0)
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#define CONFIG_SH_ETHER_PHY_ADDR (0x0)
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_SMSC 1
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_SH7734_MII (0x00) /* MII */
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
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#ifndef CONFIG_SH_ETHER
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# define CONFIG_SMC911X
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# define CONFIG_SMC911X_16_BIT
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# define CONFIG_SMC911X_BASE (0x84000000)
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#endif
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/* I2C */
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#define CONFIG_CMD_I2C
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#define CONFIG_SH_SH7734_I2C 1
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#define CONFIG_HARD_I2C 1
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_SYS_MAX_I2C_BUS 2
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#define CONFIG_SYS_I2C_MODULE 0
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x50
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#define CONFIG_SH_I2C_DATA_HIGH 4
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#define CONFIG_SH_I2C_DATA_LOW 5
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#define CONFIG_SH_I2C_CLOCK 500000000
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#define CONFIG_SH_I2C_BASE0 0xFFC70000
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#define CONFIG_SH_I2C_BASE1 0xFFC7100
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/* undef to save memory */
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#define CONFIG_SYS_LONGHELP
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/* Monitor Command Prompt */
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/* Buffer size for input from the Console */
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#define CONFIG_SYS_CBSIZE 256
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/* Buffer size for Console output */
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#define CONFIG_SYS_PBSIZE 256
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/* max args accepted for monitor commands */
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#define CONFIG_SYS_MAXARGS 16
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/* Buffer size for Boot Arguments passed to kernel */
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#define CONFIG_SYS_BARGSIZE 512
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/* List of legal baudrate settings for this board */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_SCIF 1
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#define CONFIG_CONS_SCIF3 1
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/* Suppress display of console information at boot */
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#undef CONFIG_SYS_CONSOLE_INFO_QUIET
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#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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/* SDRAM */
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#define CONFIG_SYS_SDRAM_BASE (0x88000000)
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#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 100 * 1024 * 1024)
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/* Enable alternate, more extensive, memory test */
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#undef CONFIG_SYS_ALT_MEMTEST
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/* Scratch address used by the alternate memory test */
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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/* Enable temporary baudrate change while serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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/* FLASH */
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_SYS_FLASH_CFI
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BASE (0xA0000000)
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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/* Timeout for Flash erase operations (in ms) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
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/* Timeout for Flash write operations (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
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/* Timeout for Flash set sector lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
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/* Timeout for Flash clear lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
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/*
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* Use hardware flash sectors protection instead
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* of U-Boot software protection
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*/
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#undef CONFIG_SYS_FLASH_PROTECTION
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
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/* Monitor size */
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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/* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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/* size in bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_SIZE (256)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* ENV setting */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* Board Clock */
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#if defined(CONFIG_400MHZ_MODE)
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#define CONFIG_SYS_CLK_FREQ 50000000
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#else
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#define CONFIG_SYS_CLK_FREQ 44444444
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#endif
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#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#endif /* __R0P7734_H */
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