mirror of
https://github.com/AsahiLinux/u-boot
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a74e9d899d
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
38 lines
791 B
C
38 lines
791 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020-2021 SiFive, Inc.
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*/
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#ifndef _GPIO_SIFIVE_H
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#define _GPIO_SIFIVE_H
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#define GPIO_INPUT_VAL 0x00
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#define GPIO_INPUT_EN 0x04
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#define GPIO_OUTPUT_EN 0x08
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#define GPIO_OUTPUT_VAL 0x0C
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#define GPIO_RISE_IE 0x18
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#define GPIO_RISE_IP 0x1C
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#define GPIO_FALL_IE 0x20
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#define GPIO_FALL_IP 0x24
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#define GPIO_HIGH_IE 0x28
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#define GPIO_HIGH_IP 0x2C
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#define GPIO_LOW_IE 0x30
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#define GPIO_LOW_IP 0x34
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#define GPIO_OUTPUT_XOR 0x40
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#define NR_GPIOS 16
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enum gpio_state {
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LOW,
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HIGH
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};
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/* Details about a GPIO bank */
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struct sifive_gpio_plat {
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void *base; /* address of registers in physical memory */
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};
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#define SIFIVE_GENERIC_GPIO_NR(port, index) \
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(((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
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#endif /* _GPIO_SIFIVE_H */
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