u-boot/arch/arm/dts/zynqmp-clk-ccf.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Clock specification for Xilinx ZynqMP
 *
 * (C) Copyright 2017 - 2021, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 */

#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
	fclk0: fclk0 {
		status = "okay";
		compatible = "xlnx,fclk";
		clocks = <&zynqmp_clk PL0_REF>;
	};

	fclk1: fclk1 {
		status = "okay";
		compatible = "xlnx,fclk";
		clocks = <&zynqmp_clk PL1_REF>;
	};

	fclk2: fclk2 {
		status = "okay";
		compatible = "xlnx,fclk";
		clocks = <&zynqmp_clk PL2_REF>;
	};

	fclk3: fclk3 {
		status = "okay";
		compatible = "xlnx,fclk";
		clocks = <&zynqmp_clk PL3_REF>;
	};

	pss_ref_clk: pss_ref_clk {
		u-boot,dm-pre-reloc;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	video_clk: video_clk {
		u-boot,dm-pre-reloc;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	pss_alt_ref_clk: pss_alt_ref_clk {
		u-boot,dm-pre-reloc;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	gt_crx_ref_clk: gt_crx_ref_clk {
		u-boot,dm-pre-reloc;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <108000000>;
	};

	aux_ref_clk: aux_ref_clk {
		u-boot,dm-pre-reloc;
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};
};

&zynqmp_firmware {
	zynqmp_clk: clock-controller {
		u-boot,dm-pre-reloc;
		#clock-cells = <1>;
		compatible = "xlnx,zynqmp-clk";
		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
			 <&aux_ref_clk>, <&gt_crx_ref_clk>;
		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
			      "aux_ref_clk", "gt_crx_ref_clk";
	};
};

&can0 {
	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&can1 {
	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&cpu0 {
	clocks = <&zynqmp_clk ACPU>;
};

&fpd_dma_chan1 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan2 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan3 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan4 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan5 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan6 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan7 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&fpd_dma_chan8 {
	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&gpu {
	clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
};

&lpd_dma_chan1 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan2 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan3 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan4 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan5 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan6 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan7 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&lpd_dma_chan8 {
	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&nand0 {
	clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&gem0 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gem1 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gem2 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gem3 {
	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
		 <&zynqmp_clk GEM_TSU>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};

&gpio {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&i2c0 {
	clocks = <&zynqmp_clk I2C0_REF>;
};

&i2c1 {
	clocks = <&zynqmp_clk I2C1_REF>;
};

&pcie {
	clocks = <&zynqmp_clk PCIE_REF>;
};

&qspi {
	clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&sata {
	clocks = <&zynqmp_clk SATA_REF>;
};

&sdhci0 {
	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&sdhci1 {
	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&spi0 {
	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&spi1 {
	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&ttc0 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&ttc1 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&ttc2 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&ttc3 {
	clocks = <&zynqmp_clk LPD_LSBUS>;
};

&uart0 {
	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&uart1 {
	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
};

&usb0 {
	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};

&usb1 {
	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};

&watchdog0 {
	clocks = <&zynqmp_clk WDT>;
};

&lpd_watchdog {
	clocks = <&zynqmp_clk LPD_WDT>;
};

&xilinx_ams {
	clocks = <&zynqmp_clk AMS_REF>;
};

&zynqmp_pcap {
	clocks = <&zynqmp_clk PCAP>;
};

&zynqmp_dpdma {
	clocks = <&zynqmp_clk DPDMA_REF>;
};

&zynqmp_dpsub {
	clocks = <&zynqmp_clk TOPSW_LSBUS>,
		 <&zynqmp_clk DP_AUDIO_REF>,
		 <&zynqmp_clk DP_VIDEO_REF>;
};