mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
bf1ddfc026
The DTS files had some spacing issues and they needed fixing. This
pull re-sync's the OMAP3xx related DTS files with Linux 4.13-RC5.
To keep the DTS and DTSI files clean and in sync with Linux, new
u-boot.dtsi files are added.
Signed-off-by: Adam Ford <aford173@gmail.com>
V3: The resync broke card detect on MMC1 on Logic PD's Torpedo,
so we add the cd-invert to the Torpedo's -u-boot.dtsi file.
V2: Add the u-boot.dtsi files for OMAP3, OMAP36xx, and Torpedo
Remove the need for the second patch in the series
198 lines
4.8 KiB
Text
198 lines
4.8 KiB
Text
/*
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* Device Tree Source for OMAP34xx/OMAP36xx clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cm_clocks {
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ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <0>;
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reg = <0x0a00>;
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};
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ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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ssi_ssr_fck: ssi_ssr_fck_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
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};
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ssi_sst_fck: ssi_sst_fck_3430es2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&ssi_ssr_fck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-hsotgusb-interface-clock";
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clocks = <&core_l3_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <4>;
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};
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ssi_l4_ick: ssi_l4_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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ssi_ick: ssi_ick_3430es2@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-ssi-interface-clock";
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clocks = <&ssi_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <0>;
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};
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usim_gate_fck: usim_gate_fck@c00 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&omap_96m_fck>;
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ti,bit-shift = <9>;
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reg = <0x0c00>;
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};
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sys_d2_ck: sys_d2_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sys_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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omap_96m_d2_fck: omap_96m_d2_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&omap_96m_fck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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omap_96m_d4_fck: omap_96m_d4_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&omap_96m_fck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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omap_96m_d8_fck: omap_96m_d8_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&omap_96m_fck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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omap_96m_d10_fck: omap_96m_d10_fck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&omap_96m_fck>;
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clock-mult = <1>;
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clock-div = <10>;
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};
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dpll5_m2_d4_ck: dpll5_m2_d4_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll5_m2_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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dpll5_m2_d8_ck: dpll5_m2_d8_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll5_m2_ck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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dpll5_m2_d16_ck: dpll5_m2_d16_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll5_m2_ck>;
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clock-mult = <1>;
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clock-div = <16>;
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};
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dpll5_m2_d20_ck: dpll5_m2_d20_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll5_m2_ck>;
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clock-mult = <1>;
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clock-div = <20>;
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};
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usim_mux_fck: usim_mux_fck@c40 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
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ti,bit-shift = <3>;
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reg = <0x0c40>;
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ti,index-starts-at-one;
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};
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usim_fck: usim_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&usim_gate_fck>, <&usim_mux_fck>;
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};
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usim_ick: usim_ick@c10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&wkup_l4_ick>;
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reg = <0x0c10>;
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ti,bit-shift = <9>;
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};
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};
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&cm_clockdomains {
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
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};
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wkup_clkdm: wkup_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
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<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
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<&gpt1_ick>, <&usim_ick>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
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<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
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<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
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<&ssi_ick>;
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};
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};
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