u-boot/arch/riscv/cpu/fu540
Green Wan bc8bbb77f7 riscv: cpu: fu740: clear feature disable CSR
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-05 16:11:27 +08:00
..
cache.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
cpu.c riscv: cpu: fu540: Add support for cpu fu540 2020-06-04 09:44:09 +08:00
dram.c Merge branch '2021-02-02-drop-asm_global_data-when-unused' 2021-02-15 10:16:45 -05:00
Kconfig cpu: Rename SPL_CPU_SUPPORT to SPL_CPU 2021-03-27 15:04:31 +13:00
Makefile riscv: sifive: fu540: enable all cache ways from U-Boot proper 2020-07-03 15:09:06 +08:00
spl.c riscv: cpu: fu740: clear feature disable CSR 2021-05-05 16:11:27 +08:00