mirror of
https://github.com/AsahiLinux/u-boot
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171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Simone CIANNI <simone.cianni@bticino.it>
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* Copyright (C) 2018 Raffaele RECALCATI <raffaele.recalcati@bticino.it>
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* Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IMX6SDL_DRIVE_STRENGTH 0x28
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart3_pads[] = {
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IOMUX_PADS(PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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return 0;
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}
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#endif
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struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
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.dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_cas = IMX6SDL_DRIVE_STRENGTH,
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.dram_ras = IMX6SDL_DRIVE_STRENGTH,
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.dram_reset = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00000000,
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.dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
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.dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
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};
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struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
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.grp_ddr_type = 0x000c0000,
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.grp_ddrmode_ctl = 0x00020000,
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.grp_ddrpke = 0x00000000,
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.grp_addds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
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.grp_ddrmode = 0x00020000,
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.grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
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.grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
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};
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static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
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.mem_speed = 1600,
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.density = 4,
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.width = 32,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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.SRT = 0,
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};
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static struct mx6_mmdc_calibration mx6dl_mmdc_calib = {
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.p0_mpwldectrl0 = 0x0042004b,
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.p0_mpwldectrl1 = 0x0038003c,
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.p0_mpdgctrl0 = 0x42340230,
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.p0_mpdgctrl1 = 0x0228022c,
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.p0_mprddlctl = 0x42444646,
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.p0_mpwrdlctl = 0x38382e2e,
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};
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static struct mx6_ddr_sysinfo mem_dl = {
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.dsize = 1,
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.cs1_mirror = 0,
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32,
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.ncs = 1,
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.bi_on = 1,
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.rtt_nom = 1,
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.rtt_wr = 1,
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.ralat = 5,
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.walat = 0,
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.mif3_mode = 3,
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.rst_to_cke = 0x23,
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.sde_to_rst = 0x10,
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.refsel = 1,
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.refr = 7,
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};
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static void spl_dram_init(void)
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{
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mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
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mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41k128m16jt_125);
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udelay(100);
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}
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00003f3f, &ccm->CCGR0);
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writel(0x0030fc00, &ccm->CCGR1);
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writel(0x000fc000, &ccm->CCGR2);
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writel(0x3f300000, &ccm->CCGR3);
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writel(0xff00f300, &ccm->CCGR4);
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writel(0x0f0000c3, &ccm->CCGR5);
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writel(0x000003cc, &ccm->CCGR6);
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}
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void board_init_f(ulong dummy)
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{
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ccgr_init();
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/* setup AIPS and disable watchdog */
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arch_cpu_init();
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gpr_init();
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/* iomux */
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SETUP_IOMUX_PADS(uart3_pads);
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/* setup GP timer */
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timer_init();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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/* DDR initialization */
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spl_dram_init();
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}
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