mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
1297cdb452
IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
287 lines
8.7 KiB
C
287 lines
8.7 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1043A_COMMON_H
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#define __LS1043A_COMMON_H
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_FSL_LSCH2
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#define CONFIG_LS1043A
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#define CONFIG_MP
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#define CONFIG_SYS_FSL_CLK
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#ifdef CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_HAS_SERDES
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#endif
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#ifndef CONFIG_SYS_FSL_DDR4
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#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
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#endif
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
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#define CPU_RELEASE_ADDR secondary_boot_func
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0))
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* SD boot SPL */
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xf0
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x500
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1d000
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#define CONFIG_SPL_STACK 0x1001e000
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#define CONFIG_SPL_PAD_TO 0x1d000
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0xa0000
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#endif
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/* NAND SPL */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PBL_PAD
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_ENV_SUPPORT
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#define CONFIG_SPL_WATCHDOG_SUPPORT
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#define CONFIG_SPL_I2C_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0x10000000
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#define CONFIG_SPL_MAX_SIZE 0x1a000
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#define CONFIG_SPL_STACK 0x1001d000
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#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_MONITOR_LEN 0xa0000
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#endif
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/* IFC */
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_IFC
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/*
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
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* CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
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*/
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
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#ifndef CONFIG_SYS_NO_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#endif
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1
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#define CONFIG_SYS_I2C_MXC_I2C2
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#define CONFIG_SYS_I2C_MXC_I2C3
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#define CONFIG_SYS_I2C_MXC_I2C4
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/* PCIe */
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#define CONFIG_PCI /* Enable PCI/PCIE */
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
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#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
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#define CONFIG_SYS_PCI_64BIT
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#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
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#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
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#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
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#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
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#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
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#define CONFIG_SYS_PCIE_MEM_BUS 0x40000000
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#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x40000000
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#define CONFIG_SYS_PCIE_MEM_SIZE 0x40000000 /* 1G */
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#ifdef CONFIG_PCI
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP
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#define CONFIG_E1000
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#define CONFIG_PCI_SCAN_SHOW
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#define CONFIG_CMD_PCI
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#endif
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/* Command line configuration */
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#define CONFIG_CMD_ENV
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/* MMC */
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#define CONFIG_MMC
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DOS_PARTITION
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#endif
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/* DSPI */
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#define CONFIG_FSL_DSPI
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#ifdef CONFIG_FSL_DSPI
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#define CONFIG_DM_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
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#define CONFIG_SPI_FLASH_SST /* cs1 */
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#define CONFIG_SPI_FLASH_EON /* cs2 */
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SF_DEFAULT_BUS 1
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#define CONFIG_SF_DEFAULT_CS 0
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#endif
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#endif
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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/* FMan ucode */
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#define CONFIG_SYS_DPAA_FMAN
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
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#ifdef CONFIG_NAND_BOOT
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/* Store Fman ucode at offeset 0x160000(11 blocks). */
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SD_BOOT)
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/*
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* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
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* about 1MB (2040 blocks), Env is stored after the image, and the env size is
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* 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
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*/
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#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
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#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_SYS_QE_FW_IN_SPIFLASH
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#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 1000000
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#define CONFIG_ENV_SPI_MODE 0x03
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#else
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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/* FMan fireware Pre-load address */
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#define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
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#endif
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#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
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#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
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#endif
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_ARCH_EARLY_INIT_R
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x61100000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"console=ttyAMA0,38400n8\0"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
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"earlycon=uart8250,mmio,0x21c0500"
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
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"e0000 f00000 && bootm $kernel_load"
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#else
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#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
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"$kernel_size && bootm $kernel_load"
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#endif
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#define CONFIG_BOOTDELAY 10
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/* Hash command with SHA acceleration supported in hardware */
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#ifdef CONFIG_FSL_CAAM
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#define CONFIG_CMD_HASH
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#define CONFIG_SHA_HW_ACCEL
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#endif
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#endif /* __LS1043A_COMMON_H */
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