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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
77 lines
1.7 KiB
ArmAsm
77 lines
1.7 KiB
ArmAsm
/*
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* Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307USA
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*/
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#include <config.h>
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#include <command.h>
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#include <74xx_7xx.h>
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#include <version.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_CMD_KGDB)
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/*
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* cache flushing routines for kgdb
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*/
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.globl kgdb_flush_cache_all
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kgdb_flush_cache_all:
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lis r3,0
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addis r4,r0,0x0040
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kgdb_flush_loop:
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lwz r5,0(r3)
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addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
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cmp 0,0,r3,r4
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bne kgdb_flush_loop
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SYNC
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mfspr r3,1008
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ori r3,r3,0x8800
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mtspr 1008,r3
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sync
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blr
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.globl kgdb_flush_cache_range
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kgdb_flush_cache_range:
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li r5,CONFIG_SYS_CACHELINE_SIZE-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
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bdnz 2b
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SYNC
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blr
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#endif
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