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bc13472867
On some future SoCs, some per-drive-group features became per-pin features. Move all type definitions early in the header so they can be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
215 lines
5.1 KiB
C
215 lines
5.1 KiB
C
/*
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* (C) Copyright 2010-2014
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA_PINMUX_H_
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#define _TEGRA_PINMUX_H_
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#include <asm/arch/tegra.h>
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/* The pullup/pulldown state of a pin group */
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enum pmux_pull {
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PMUX_PULL_NORMAL = 0,
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PMUX_PULL_DOWN,
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PMUX_PULL_UP,
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};
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/* Defines whether a pin group is tristated or in normal operation */
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enum pmux_tristate {
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PMUX_TRI_NORMAL = 0,
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PMUX_TRI_TRISTATE = 1,
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};
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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enum pmux_pin_io {
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PMUX_PIN_OUTPUT = 0,
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PMUX_PIN_INPUT = 1,
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PMUX_PIN_NONE,
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};
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_LOCK
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enum pmux_pin_lock {
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PMUX_PIN_LOCK_DEFAULT = 0,
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PMUX_PIN_LOCK_DISABLE,
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PMUX_PIN_LOCK_ENABLE,
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};
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_OD
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enum pmux_pin_od {
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PMUX_PIN_OD_DEFAULT = 0,
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PMUX_PIN_OD_DISABLE,
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PMUX_PIN_OD_ENABLE,
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};
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
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enum pmux_pin_ioreset {
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PMUX_PIN_IO_RESET_DEFAULT = 0,
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PMUX_PIN_IO_RESET_DISABLE,
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PMUX_PIN_IO_RESET_ENABLE,
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};
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
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enum pmux_pin_rcv_sel {
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PMUX_PIN_RCV_SEL_DEFAULT = 0,
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PMUX_PIN_RCV_SEL_NORMAL,
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PMUX_PIN_RCV_SEL_HIGH,
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};
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
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/* Defines a pin group cfg's low-power mode select */
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enum pmux_lpmd {
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PMUX_LPMD_X8 = 0,
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PMUX_LPMD_X4,
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PMUX_LPMD_X2,
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PMUX_LPMD_X,
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PMUX_LPMD_NONE = -1,
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};
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
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/* Defines whether a pin group cfg's schmidt is enabled or not */
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enum pmux_schmt {
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PMUX_SCHMT_DISABLE = 0,
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PMUX_SCHMT_ENABLE = 1,
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PMUX_SCHMT_NONE = -1,
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};
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_HSM
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/* Defines whether a pin group cfg's high-speed mode is enabled or not */
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enum pmux_hsm {
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PMUX_HSM_DISABLE = 0,
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PMUX_HSM_ENABLE = 1,
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PMUX_HSM_NONE = -1,
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};
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#endif
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/*
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* This defines the configuration for a pin, including the function assigned,
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* pull up/down settings and tristate settings. Having set up one of these
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* you can call pinmux_config_pingroup() to configure a pin in one step. Also
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* available is pinmux_config_table() to configure a list of pins.
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*/
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struct pmux_pingrp_config {
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u32 pingrp:16; /* pin group PMUX_PINGRP_... */
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u32 func:8; /* function to assign PMUX_FUNC_... */
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u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
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u32 tristate:2; /* tristate or normal PMUX_TRI_... */
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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u32 io:2; /* input or output PMUX_PIN_... */
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_LOCK
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u32 lock:2; /* lock enable/disable PMUX_PIN... */
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_OD
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u32 od:2; /* open-drain or push-pull driver */
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
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u32 ioreset:2; /* input/output reset PMUX_PIN... */
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#endif
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#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
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u32 rcv_sel:2; /* select between High and Normal */
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/* VIL/VIH receivers */
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#endif
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};
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#ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
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/* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
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void pinmux_set_tristate_input_clamping(void);
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void pinmux_clear_tristate_input_clamping(void);
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#endif
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/* Set the mux function for a pin group */
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void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
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/* Set the pull up/down feature for a pin group */
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void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
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/* Set a pin group to tristate */
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void pinmux_tristate_enable(enum pmux_pingrp pin);
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/* Set a pin group to normal (non tristate) */
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void pinmux_tristate_disable(enum pmux_pingrp pin);
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#ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
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/* Set a pin group as input or output */
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void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
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#endif
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/**
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* Configure a list of pin groups
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*
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* @param config List of config items
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* @param len Number of config items in list
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*/
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void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
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int len);
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#ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
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#define PMUX_SLWF_MIN 0
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#define PMUX_SLWF_MAX 3
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#define PMUX_SLWF_NONE -1
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#define PMUX_SLWR_MIN 0
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#define PMUX_SLWR_MAX 3
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#define PMUX_SLWR_NONE -1
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#define PMUX_DRVUP_MIN 0
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#define PMUX_DRVUP_MAX 127
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#define PMUX_DRVUP_NONE -1
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#define PMUX_DRVDN_MIN 0
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#define PMUX_DRVDN_MAX 127
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#define PMUX_DRVDN_NONE -1
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/*
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* This defines the configuration for a pin group's pad control config
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*/
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struct pmux_drvgrp_config {
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u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
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u32 slwf:3; /* falling edge slew */
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u32 slwr:3; /* rising edge slew */
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u32 drvup:8; /* pull-up drive strength */
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u32 drvdn:8; /* pull-down drive strength */
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#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
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u32 lpmd:3; /* low-power mode selection */
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
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u32 schmt:2; /* schmidt enable */
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#endif
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#ifdef TEGRA_PMX_GRPS_HAVE_HSM
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u32 hsm:2; /* high-speed mode enable */
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#endif
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};
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/**
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* Set the GP pad configs
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*
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* @param config List of config items
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* @param len Number of config items in list
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*/
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void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
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int len);
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#endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
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struct pmux_pingrp_desc {
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u8 funcs[4];
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#if defined(CONFIG_TEGRA20)
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u8 ctl_id;
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u8 pull_id;
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#endif /* CONFIG_TEGRA20 */
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};
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extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
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#endif /* _TEGRA_PINMUX_H_ */
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