u-boot/drivers/pci/Kconfig
Stephen Warren bbc5b36b25 pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.

On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-15 10:26:13 -07:00

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menu "PCI"
config DM_PCI
bool "Enable driver mode for PCI"
depends on DM
help
Use driver model for PCI. Driver model is the new method for
orgnising devices in U-Boot. For PCI, driver model keeps track of
available PCI devices, allows scanning of PCI buses and provides
device configuration support.
config DM_PCI_COMPAT
bool "Enable compatible functions for PCI"
depends on DM_PCI
help
Enable compatibility functions for PCI so that old code can be used
with CONFIG_DM_PCI enabled. This should be used as an interim
measure when porting a board to use driver model for PCI. Once the
board is fully supported, this option should be disabled.
config PCI_SANDBOX
bool "Sandbox PCI support"
depends on SANDBOX && DM_PCI
help
Support PCI on sandbox, as an emulated bus. This permits testing of
PCI feature such as bus scanning, device configuration and device
access. The available (emulated) devices are defined statically in
the device tree but the normal PCI scan technique is used to find
then.
config PCI_TEGRA
bool "Tegra PCI support"
depends on TEGRA
depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
help
Enable support for the PCIe controller found on some generations of
Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
with a total of 5 lanes. Some boards require this for Ethernet
support to work (e.g. beaver, jetson-tk1).
endmenu