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723f8359c1
Working with HAB on the i.MX7 we've encountered a case where a board that
successfully authenticates u-boot when booting Linux via OPTEE subsequently
fails to properly bring up the RTC.
The RTC registers live in the low-power block of the Secure Non-Volatile
Storage (SNVS) block.
The root cause of the error has been traced to the HAB handing off the
SNVS-RTC in a state where HPCOMR::NPSWA_EN = 0 in other words where the
Non-Privileged Software Access Enable bit is zero. In ordinary
circumstances this is OK since we typically do not run in TZ mode, however
when we boot via HAB and enablng TrustZone, it is required to set
HPCOMR::NPSWA_EN = 1 in order for the upstream Linux driver to have
sufficient permissions to manipulate the SNVS-LP block.
On our reference board it is the difference between Linux doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000021 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000000 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x80002100 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: rtc core: registered
30370000.snvs:snvs-rtc-lp as rtc0
snvs_rtc 30370000.snvs:snvs-rtc-lp: setting system clock to2018-04-01 00:51:04 UTC (1522543864)
and doing this:
root@imx7s-warp-mbl:~# dmesg | grep rtc
snvs_rtc_enable read 0x00000000 from SNVS_LPLR @ 0x00000034
snvs_rtc_enable read 0x00000020 from SNVS_LPCR @ 0x00000038
snvs_rtc_enable read 0x00000001 from SNVS_HPLR @ 0x00000000
snvs_rtc_enable read 0x00002020 from SNVS_HPCOMR @ 0x00000004
snvs_rtc 30370000.snvs:snvs-rtc-lp: failed to enable rtc -110
snvs_rtc: probe of 30370000.snvs:snvs-rtc-lp failed with error -110
hctosys: unable to open rtc device (rtc0)
Note bit 1 of LPCR is not set in the second case and is set in the first
case and that bit 31 of HPCOMR is set in the second case but not in the
first.
Setting NPSWA_EN in HPCOMR allows us to boot through enabling TrustZone
and continue onto the kernel. The kernel then has the necessary permissions
to set LPCR::SRTC_ENV (RTC enable in the LP command register) whereas in
contrast - in the failing case the non-privileged kernel cannot do so.
This patch adds a simple init_snvs() call which sets the permission-bit
called from soc.c for the i.MX7. It may be possible, safe and desirable to
perform this on other i.MX processors but for now this is only tested on
i.MX7 as working.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
134 lines
3.5 KiB
C
134 lines
3.5 KiB
C
/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/io.h>
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#include <asm/mach-imx/regs-common.h>
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#include <common.h>
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#include "../arch-imx/cpu.h"
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#define soc_rev() (get_cpu_rev() & 0xFF)
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#define is_soc_rev(rev) (soc_rev() == rev)
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12) & 0xff)
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#define soc_type(rev) (((rev) >> 12) & 0xf0)
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/* both macros return/take MXC_CPU_ constants */
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#define get_cpu_type() (cpu_type(get_cpu_rev()))
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#define get_soc_type() (soc_type(get_cpu_rev()))
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#define is_cpu_type(cpu) (get_cpu_type() == cpu)
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#define is_soc_type(soc) (get_soc_type() == soc)
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#define is_mx6() (is_soc_type(MXC_SOC_MX6))
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#define is_mx7() (is_soc_type(MXC_SOC_MX7))
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#define is_mx8m() (is_soc_type(MXC_SOC_MX8M))
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#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
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#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
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#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6dl() (is_cpu_type(MXC_CPU_MX6DL))
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#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
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#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
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#define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO))
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#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
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#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL))
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#define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL))
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#define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
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#ifdef CONFIG_MX6
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#define IMX6_SRC_GPR10_BMODE BIT(28)
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#define IMX6_BMODE_MASK GENMASK(7, 0)
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#define IMX6_BMODE_SHIFT 4
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#define IMX6_BMODE_EMI_MASK BIT(3)
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#define IMX6_BMODE_EMI_SHIFT 3
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#define IMX6_BMODE_SERIAL_ROM_MASK GENMASK(26, 24)
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#define IMX6_BMODE_SERIAL_ROM_SHIFT 24
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enum imx6_bmode_serial_rom {
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IMX6_BMODE_ECSPI1,
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IMX6_BMODE_ECSPI2,
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IMX6_BMODE_ECSPI3,
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IMX6_BMODE_ECSPI4,
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IMX6_BMODE_ECSPI5,
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IMX6_BMODE_I2C1,
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IMX6_BMODE_I2C2,
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IMX6_BMODE_I2C3,
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};
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enum imx6_bmode_emi {
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IMX6_BMODE_ONENAND,
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IMX6_BMODE_NOR,
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};
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enum imx6_bmode {
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IMX6_BMODE_EMI,
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#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
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IMX6_BMODE_QSPI,
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IMX6_BMODE_RESERVED,
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#else
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IMX6_BMODE_RESERVED,
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IMX6_BMODE_SATA,
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#endif
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IMX6_BMODE_SERIAL_ROM,
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IMX6_BMODE_SD,
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IMX6_BMODE_ESD,
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IMX6_BMODE_MMC,
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IMX6_BMODE_EMMC,
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IMX6_BMODE_NAND_MIN,
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IMX6_BMODE_NAND_MAX = 0xf,
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};
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static inline u8 imx6_is_bmode_from_gpr9(void)
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{
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return readl(&src_base->gpr10) & IMX6_SRC_GPR10_BMODE;
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}
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u32 imx6_src_get_boot_mode(void);
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void gpr_init(void);
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#endif /* CONFIG_MX6 */
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u32 get_nr_cpus(void);
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u32 get_cpu_rev(void);
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u32 get_cpu_speed_grade_hz(void);
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u32 get_cpu_temp_grade(int *minc, int *maxc);
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const char *get_imx_type(u32 imxtype);
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u32 imx_ddr_size(void);
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void sdelay(unsigned long);
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void set_chipselect_size(int const);
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void init_aips(void);
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void init_src(void);
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void init_snvs(void);
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void imx_wdog_disable_powerdown(void);
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int board_mmc_get_env_dev(int devno);
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int nxp_board_rev(void);
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char nxp_board_rev_string(void);
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int fecmxc_initialize(bd_t *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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void lcdif_power_down(void);
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
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unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
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unsigned long reg1, unsigned long reg2);
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#endif
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