u-boot/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi
Patrick Delaunay b90f0e7c37 stm32mp1: change STGEN clock source to HSE
No more use static frequency HSI = 64MHz for STGEN clock
but HSE (with higher accurency) by default.

Need to remove CONFIG_SYS_HZ_CLOCK as arch timer frequency
is provided at boot by BootRom and cp15 cntfrq and modified
during clock tree initialization if needed.

When HSI is no more used by any device, this internal
oscillator can be switched off to reduce consumption.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-04-06 20:45:28 -04:00

155 lines
2.1 KiB
Text

/*
* Copyright : STMicroelectronics 2018
*
* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
*/
#include <dt-bindings/clock/stm32mp1-clksrc.h>
#include "stm32mp157-u-boot.dtsi"
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
/ {
aliases {
mmc0 = &sdmmc1;
mmc1 = &sdmmc2;
i2c3 = &i2c4;
};
};
&uart4_pins_a {
u-boot,dm-pre-reloc;
pins1 {
u-boot,dm-pre-reloc;
};
pins2 {
u-boot,dm-pre-reloc;
};
};
&i2c4_pins_a {
u-boot,dm-pre-reloc;
pins {
u-boot,dm-pre-reloc;
};
};
&uart4 {
u-boot,dm-pre-reloc;
};
&i2c4 {
u-boot,dm-pre-reloc;
};
&pmic {
u-boot,dm-pre-reloc;
};
/* CLOCK init */
&rcc_clk {
st,clksrc = <
CLK_MPU_PLL1P
CLK_AXI_PLL2P
CLK_MCU_PLL3P
CLK_PLL12_HSE
CLK_PLL3_HSE
CLK_PLL4_HSE
CLK_RTC_LSE
CLK_MCO1_DISABLED
CLK_MCO2_DISABLED
>;
st,clkdiv = <
1 /*MPU*/
0 /*AXI*/
0 /*MCU*/
1 /*APB1*/
1 /*APB2*/
1 /*APB3*/
1 /*APB4*/
2 /*APB5*/
23 /*RTC*/
0 /*MCO1*/
0 /*MCO2*/
>;
st,pkcs = <
CLK_CKPER_DISABLED
CLK_SDMMC12_PLL3R
CLK_STGEN_HSE
CLK_I2C46_PCLK5
CLK_I2C12_PCLK1
CLK_SDMMC3_PLL3R
CLK_I2C35_PCLK1
CLK_UART1_PCLK5
CLK_UART24_PCLK1
CLK_UART35_PCLK1
CLK_UART6_PCLK2
CLK_UART78_PCLK1
>;
/* VCO = 1300.0 MHz => P = 650 (CPU) */
pll1: st,pll@0 {
cfg = < 2 80 0 0 0 PQR(1,0,0) >;
frac = < 0x800 >;
u-boot,dm-pre-reloc;
};
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
pll2: st,pll@1 {
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
frac = < 0x1400 >;
u-boot,dm-pre-reloc;
};
/* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */
pll3: st,pll@2 {
cfg = < 3 128 3 20 7 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
/* VCO = 508.0 MHz => P = 56, Q = 56, R = 56 */
pll4: st,pll@3 {
cfg = < 5 126 8 8 8 PQR(1,1,1) >;
u-boot,dm-pre-reloc;
};
};
/* SPL part **************************************/
/* MMC1 boot */
&sdmmc1_b4_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc1_dir_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc1 {
u-boot,dm-spl;
};
/* MMC2 boot */
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_a {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};
&sdmmc2 {
u-boot,dm-spl;
};