mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
32af1c0b3f
Prepare for linking setup_sata only when CONFIG_SATA/CONFIG_SPL_SATA is defined. Signed-off-by: Troy Kisky <troykiskyboundary@gmail.com>
498 lines
12 KiB
C
498 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Freescale Semiconductor, Inc.
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* Copyright (C) 2014 O.S. Systems Software LTDA.
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*
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*/
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#include <common.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/video.h>
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#include <asm/mach-imx/sata.h>
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#include <asm/io.h>
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#include <env.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <phy.h>
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#include <i2c.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
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#define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
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#define REV_DETECTION IMX_GPIO_NR(2, 28)
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/* Speed defined in Kconfig is only applicable when not using DM_I2C. */
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#if CONFIG_IS_ENABLED(DM_I2C)
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#define I2C1_SPEED_NON_DM 0
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#define I2C2_SPEED_NON_DM 0
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#else
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#define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
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#define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
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#endif
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static bool with_pmic;
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_pads[] = {
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/* AR8031 PHY Reset */
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IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
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/* AR8035 POWER */
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IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static iomux_v3_cfg_t const rev_detection_pad[] = {
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IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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};
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static void setup_iomux_uart(void)
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{
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SETUP_IOMUX_PADS(uart1_pads);
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}
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static void setup_iomux_enet(void)
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{
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SETUP_IOMUX_PADS(enet_pads);
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if (with_pmic) {
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SETUP_IOMUX_PADS(enet_ar8035_power_pads);
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/* enable AR8035 POWER */
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gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
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gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
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}
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/* wait until 3.3V of PHY and clock become stable */
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mdelay(10);
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/* Reset AR8031 PHY */
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gpio_request(ETH_PHY_RESET, "PHY_RESET");
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gpio_direction_output(ETH_PHY_RESET, 0);
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mdelay(10);
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gpio_set_value(ETH_PHY_RESET, 1);
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udelay(100);
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}
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static int ar8031_phy_fixup(struct phy_device *phydev)
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{
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unsigned short val;
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int mask;
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/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
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phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
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if (with_pmic)
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mask = 0xffe7; /* AR8035 */
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else
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mask = 0xffe3; /* AR8031 */
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val &= mask;
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val |= 0x18;
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phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
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/* introduce tx clock delay */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
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val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
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val |= 0x0100;
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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ar8031_phy_fixup(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#if defined(CONFIG_VIDEO_IPUV3)
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struct i2c_pads_info mx6q_i2c2_pad_info = {
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.scl = {
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.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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struct i2c_pads_info mx6dl_i2c2_pad_info = {
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.scl = {
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.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 12)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(4, 13)
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}
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};
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struct i2c_pads_info mx6q_i2c3_pad_info = {
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.scl = {
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.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(1, 5)
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},
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.sda = {
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.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(7, 11)
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}
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};
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struct i2c_pads_info mx6dl_i2c3_pad_info = {
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.scl = {
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.i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(1, 5)
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},
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.sda = {
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.i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
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| MUX_PAD_CTRL(I2C_PAD_CTRL),
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.gp = IMX_GPIO_NR(7, 11)
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}
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};
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static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
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IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
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IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
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IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
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IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
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IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
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IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
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IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
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IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
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IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
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IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
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IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
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IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
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IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
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IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
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IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
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IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
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IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
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IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
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IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
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IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
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IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
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IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
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IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
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IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
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};
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static void do_enable_hdmi(struct display_info_t const *dev)
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{
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imx_enable_hdmi_phy();
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}
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static int detect_i2c(struct display_info_t const *dev)
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{
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#if CONFIG_IS_ENABLED(DM_I2C)
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struct udevice *bus, *udev;
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int rc;
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rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
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if (rc)
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return rc;
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rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
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if (rc)
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return 0;
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return 1;
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#else
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return (0 == i2c_set_bus_num(dev->bus)) &&
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(0 == i2c_probe(dev->addr));
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#endif
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}
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static void enable_fwadapt_7wvga(struct display_info_t const *dev)
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{
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SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
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gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
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gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
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gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
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gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
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}
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struct display_info_t const displays[] = {{
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.bus = -1,
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.addr = 0,
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.pixfmt = IPU_PIX_FMT_RGB24,
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.detect = detect_hdmi,
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.enable = do_enable_hdmi,
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.mode = {
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.name = "HDMI",
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.refresh = 60,
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.xres = 1024,
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.yres = 768,
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.pixclock = 15385,
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.left_margin = 220,
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.right_margin = 40,
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.upper_margin = 21,
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.lower_margin = 7,
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.hsync_len = 60,
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.vsync_len = 10,
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.sync = FB_SYNC_EXT,
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.vmode = FB_VMODE_NONINTERLACED
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} }, {
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.bus = 1,
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.addr = 0x10,
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.pixfmt = IPU_PIX_FMT_RGB666,
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.detect = detect_i2c,
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.enable = enable_fwadapt_7wvga,
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.mode = {
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.name = "FWBADAPT-LCD-F07A-0102",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 33260,
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.left_margin = 128,
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.right_margin = 128,
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.upper_margin = 22,
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.lower_margin = 22,
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.hsync_len = 1,
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.vsync_len = 1,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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static void setup_display(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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int reg;
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enable_ipu_clock();
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imx_setup_hdmi();
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reg = readl(&mxc_ccm->chsccdr);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0
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<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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/* Disable LCD backlight */
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SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
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gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
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gpio_direction_input(IMX_GPIO_NR(4, 20));
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}
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#endif /* CONFIG_VIDEO_IPUV3 */
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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if (CONFIG_IS_ENABLED(SATA))
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setup_sata();
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return 0;
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}
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#define PMIC_I2C_BUS 2
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int power_init_board(void)
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{
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struct udevice *dev;
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int reg, ret;
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ret = pmic_get("pfuze100@8", &dev);
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if (ret < 0) {
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debug("pmic_get() ret %d\n", ret);
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return 0;
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}
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reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
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if (reg < 0) {
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debug("pmic_reg_read() ret %d\n", reg);
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return 0;
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}
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printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
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with_pmic = true;
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/* Set VGEN2 to 1.5V and enable */
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reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
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reg &= ~(LDO_VOL_MASK);
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reg |= (LDOA_1_50V | (1 << (LDO_EN)));
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pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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{"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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static bool is_revc1(void)
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{
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SETUP_IOMUX_PADS(rev_detection_pad);
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gpio_request(REV_DETECTION, "REV_DETECT");
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gpio_direction_input(REV_DETECTION);
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if (gpio_get_value(REV_DETECTION))
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return true;
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else
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return false;
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}
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static bool is_revd1(void)
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{
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if (with_pmic)
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return true;
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else
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return false;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_CMD_BMODE
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add_board_boot_modes(board_boot_modes);
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#endif
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (is_mx6dqp())
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env_set("board_rev", "MX6QP");
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else if (is_mx6dq())
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env_set("board_rev", "MX6Q");
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else
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env_set("board_rev", "MX6DL");
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if (is_revd1())
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env_set("board_name", "D1");
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else if (is_revc1())
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env_set("board_name", "C1");
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else
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env_set("board_name", "B1");
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#endif
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setup_iomux_enet();
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if (is_revd1())
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puts("Board: Wandboard rev D1\n");
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else if (is_revc1())
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puts("Board: Wandboard rev C1\n");
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else
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puts("Board: Wandboard rev B1\n");
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#if defined(CONFIG_VIDEO_IPUV3)
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setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
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if (is_mx6dq() || is_mx6dqp()) {
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setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
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setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
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} else {
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setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
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setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
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}
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setup_display();
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#endif
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return 0;
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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if (is_mx6dq()) {
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if (!strcmp(name, "imx6q-wandboard-revd1"))
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return 0;
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} else if (is_mx6dqp()) {
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if (!strcmp(name, "imx6qp-wandboard-revd1"))
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return 0;
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} else if (is_mx6dl() || is_mx6solo()) {
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if (!strcmp(name, "imx6dl-wandboard-revd1"))
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return 0;
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}
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return -EINVAL;
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}
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#endif
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