u-boot/drivers/ddr/marvell/a38x/mv_ddr_training_db.h
Chris Packham ebb1a59325 ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").

The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:

  ddr3: add missing txsdll parameter
  ddr3: fix tfaw timimg parameter
  ddr3: fix trrd timimg parameter
  merge ddr3 topology header file with mv_ddr_topology one
  mv_ddr: a38x: fix zero memory size scrubbing issue

The upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdef

    find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
        xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
                 -UCONFIG_APN806 -UCONFIG_MC_STATIC \
                 -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
                 -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
                 -UA70X0

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-12-08 16:19:40 +01:00

40 lines
1 KiB
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2018 Marvell International Ltd.
*/
#ifndef _MV_DDR_TRAINING_DB_H
#define _MV_DDR_TRAINING_DB_H
#include "mv_ddr_topology.h"
/* in ns */
#define TREFI_LOW 7800
#define TREFI_HIGH 3900
enum mv_ddr_page_size {
MV_DDR_PAGE_SIZE_1K = 1,
MV_DDR_PAGE_SIZE_2K
};
struct mv_ddr_page_element {
/* 8-bit bus width page size */
enum mv_ddr_page_size page_size_8bit;
/* 16-bit bus width page size */
enum mv_ddr_page_size page_size_16bit;
};
/* cas latency value per frequency */
struct mv_ddr_cl_val_per_freq {
unsigned int cl_val[MV_DDR_FREQ_LAST];
};
u32 mv_ddr_rfc_get(u32 mem);
unsigned int *mv_ddr_freq_tbl_get(void);
u32 mv_ddr_freq_get(enum mv_ddr_freq freq);
u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size);
unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element);
u32 mv_ddr_cl_val_get(u32 index, u32 freq);
u32 mv_ddr_cwl_val_get(u32 index, u32 freq);
#endif /* _MV_DDR_TRAINING_DB_H */