mirror of
https://github.com/AsahiLinux/u-boot
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136 lines
4.3 KiB
C
136 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
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* All rights reserved.
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*/
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#include <asm/cache.h>
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#include <altera.h>
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#include <image.h>
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#include <linux/bitops.h>
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#ifndef _FPGA_MANAGER_ARRIA10_H_
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#define _FPGA_MANAGER_ARRIA10_H_
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
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ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29)
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#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0)
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1)
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2)
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8)
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16)
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#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24)
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#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0)
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#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16)
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#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24)
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#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0)
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#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8)
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#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
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#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
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#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
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#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
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#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
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#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
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#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
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#ifndef __ASSEMBLY__
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struct socfpga_fpga_manager {
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u32 _pad_0x0_0x7[2];
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u32 dclkcnt;
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u32 dclkstat;
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u32 gpo;
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u32 gpi;
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u32 misci;
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u32 _pad_0x1c_0x2f[5];
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u32 emr_data0;
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u32 emr_data1;
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u32 emr_data2;
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u32 emr_data3;
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u32 emr_data4;
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u32 emr_data5;
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u32 emr_valid;
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u32 emr_en;
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u32 jtag_config;
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u32 jtag_status;
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u32 jtag_kick;
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u32 _pad_0x5c_0x5f;
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u32 jtag_data_w;
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u32 jtag_data_r;
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u32 _pad_0x68_0x6f[2];
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u32 imgcfg_ctrl_00;
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u32 imgcfg_ctrl_01;
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u32 imgcfg_ctrl_02;
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u32 _pad_0x7c_0x7f;
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u32 imgcfg_stat;
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u32 intr_masked_status;
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u32 intr_mask;
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u32 intr_polarity;
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u32 dma_config;
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u32 imgcfg_fifo_status;
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};
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enum rbf_type {
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unknown,
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periph_section,
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core_section
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};
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enum rbf_security {
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invalid,
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unencrypted,
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encrypted
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};
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struct rbf_info {
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enum rbf_type section;
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enum rbf_security security;
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};
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struct fpga_loadfs_info {
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fpga_fs_info *fpga_fsinfo;
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u32 remaining;
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u32 offset;
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struct rbf_info rbfinfo;
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};
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/* Functions */
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int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
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int fpgamgr_program_finish(void);
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int is_fpgamgr_user_mode(void);
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int fpgamgr_wait_early_user_mode(void);
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const char *get_fpga_filename(void);
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int is_fpgamgr_early_user_mode(void);
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int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
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u32 offset);
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void fpgamgr_program(const void *buf, size_t bsize, u32 offset);
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#endif /* __ASSEMBLY__ */
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#endif /* _FPGA_MANAGER_ARRIA10_H_ */
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