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https://github.com/AsahiLinux/u-boot
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7f899da901
This driver is needed for XHCI to work on the Allwinner H6 SoC. The driver is copied from Linux v5.10. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
171 lines
4.3 KiB
C
171 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Allwinner sun50i(H6) USB 3.0 phy driver
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*
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* Copyright (C) 2020 Samuel Holland <samuel@sholland.org>
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*
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* Based on the Linux driver, which is:
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*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* Based on phy-sun9i-usb.c, which is:
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*
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* Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
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*
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* Based on code from Allwinner BSP, which is:
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*
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* Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <generic-phy.h>
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#include <linux/bitops.h>
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#include <reset.h>
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/* Interface Status and Control Registers */
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#define SUNXI_ISCR 0x00
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#define SUNXI_PIPE_CLOCK_CONTROL 0x14
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#define SUNXI_PHY_TUNE_LOW 0x18
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#define SUNXI_PHY_TUNE_HIGH 0x1c
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#define SUNXI_PHY_EXTERNAL_CONTROL 0x20
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/* USB2.0 Interface Status and Control Register */
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#define SUNXI_ISCR_FORCE_VBUS (3 << 12)
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/* PIPE Clock Control Register */
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#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6)
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/* PHY External Control Register */
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#define SUNXI_PEC_EXTERN_VBUS (3 << 1)
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#define SUNXI_PEC_SSC_EN (1 << 24)
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#define SUNXI_PEC_REF_SSP_EN (1 << 26)
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/* PHY Tune High Register */
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#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19)
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#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19)
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#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13)
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#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13)
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#define SUNXI_TX_SWING_FULL(n) ((n) << 6)
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#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6)
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#define SUNXI_LOS_BIAS(n) ((n) << 3)
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#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3)
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#define SUNXI_TXVBOOSTLVL(n) ((n) << 0)
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#define SUNXI_TXVBOOSTLVL_MASK GENMASK(2, 0)
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struct sun50i_usb3_phy_priv {
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void __iomem *regs;
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struct reset_ctl reset;
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struct clk clk;
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};
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static void sun50i_usb3_phy_open(struct sun50i_usb3_phy_priv *phy)
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{
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u32 val;
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val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
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val |= SUNXI_PEC_EXTERN_VBUS;
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val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
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writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
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val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
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val |= SUNXI_PCC_PIPE_CLK_OPEN;
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writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
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val = readl(phy->regs + SUNXI_ISCR);
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val |= SUNXI_ISCR_FORCE_VBUS;
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writel(val, phy->regs + SUNXI_ISCR);
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/*
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* All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
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* registers are directly taken from the BSP USB3 driver from
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* Allwiner.
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*/
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writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
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val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
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val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
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SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
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SUNXI_TX_DEEMPH_3P5DB_MASK);
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val |= SUNXI_TXVBOOSTLVL(0x7);
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val |= SUNXI_LOS_BIAS(0x7);
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val |= SUNXI_TX_SWING_FULL(0x55);
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val |= SUNXI_TX_DEEMPH_6DB(0x20);
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val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
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writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
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}
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static int sun50i_usb3_phy_init(struct phy *phy)
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{
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struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev);
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int ret;
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ret = clk_prepare_enable(&priv->clk);
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if (ret)
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return ret;
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ret = reset_deassert(&priv->reset);
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if (ret) {
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clk_disable_unprepare(&priv->clk);
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return ret;
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}
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sun50i_usb3_phy_open(priv);
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return 0;
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}
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static int sun50i_usb3_phy_exit(struct phy *phy)
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{
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struct sun50i_usb3_phy_priv *priv = dev_get_priv(phy->dev);
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reset_assert(&priv->reset);
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clk_disable_unprepare(&priv->clk);
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return 0;
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}
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static const struct phy_ops sun50i_usb3_phy_ops = {
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.init = sun50i_usb3_phy_init,
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.exit = sun50i_usb3_phy_exit,
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};
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static int sun50i_usb3_phy_probe(struct udevice *dev)
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{
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struct sun50i_usb3_phy_priv *priv = dev_get_priv(dev);
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int ret;
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret) {
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dev_err(dev, "failed to get phy clock\n");
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return ret;
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}
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ret = reset_get_by_index(dev, 0, &priv->reset);
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if (ret) {
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dev_err(dev, "failed to get reset control\n");
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return ret;
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}
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priv->regs = (void __iomem *)dev_read_addr(dev);
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if (IS_ERR(priv->regs))
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return PTR_ERR(priv->regs);
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return 0;
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}
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static const struct udevice_id sun50i_usb3_phy_ids[] = {
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{ .compatible = "allwinner,sun50i-h6-usb3-phy" },
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{ },
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};
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U_BOOT_DRIVER(sun50i_usb3_phy) = {
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.name = "sun50i-usb3-phy",
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.id = UCLASS_PHY,
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.of_match = sun50i_usb3_phy_ids,
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.ops = &sun50i_usb3_phy_ops,
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.probe = sun50i_usb3_phy_probe,
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.priv_auto = sizeof(struct sun50i_usb3_phy_priv),
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};
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