mirror of
https://github.com/AsahiLinux/u-boot
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9f603e2fff
Device tree alignment with kernel v6.0-rc4. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
260 lines
5.7 KiB
Text
260 lines
5.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/memory/stm32-sdram.h>
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/{
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clocks {
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u-boot,dm-pre-reloc;
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};
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aliases {
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/* Aliases for gpios so as to use sequence */
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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spi0 = &qspi;
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};
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soc {
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u-boot,dm-pre-reloc;
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fmc: fmc@A0000000 {
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compatible = "st,stm32-fmc";
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reg = <0xa0000000 0x1000>;
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clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
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st,syscfg = <&syscfg>;
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pinctrl-0 = <&fmc_pins_d32>;
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pinctrl-names = "default";
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st,mem_remap = <4>;
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u-boot,dm-pre-reloc;
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/*
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* Memory configuration from sdram
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* MICRON MT48LC4M32B2B5-6A
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*/
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bank0: bank@0 {
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st,sdram-control = /bits/ 8 <NO_COL_8
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NO_ROW_12
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MWIDTH_32
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BANKS_4
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CAS_3
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SDCLK_2
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RD_BURST_EN
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RD_PIPE_DL_0>;
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st,sdram-timing = /bits/ 8 <TMRD_2
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TXSR_6
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TRAS_4
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TRC_6
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TWR_2
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TRP_2
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TRCD_2>;
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st,sdram-refcount = < 1292 >;
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};
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};
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qspi: spi@A0001000 {
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compatible = "st,stm32f469-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
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reg-names = "qspi", "qspi_mm";
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interrupts = <91>;
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spi-max-frequency = <108000000>;
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clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
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resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
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pinctrl-0 = <&qspi_pins>;
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};
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};
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};
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&clk_hse {
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u-boot,dm-pre-reloc;
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};
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&clk_i2s_ckin {
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u-boot,dm-pre-reloc;
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};
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&clk_lse {
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u-boot,dm-pre-reloc;
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};
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&gpioa {
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u-boot,dm-pre-reloc;
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};
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&gpiob {
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u-boot,dm-pre-reloc;
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};
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&gpioc {
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u-boot,dm-pre-reloc;
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};
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&gpiod {
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u-boot,dm-pre-reloc;
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};
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&gpioe {
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u-boot,dm-pre-reloc;
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};
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&gpiof {
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u-boot,dm-pre-reloc;
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};
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&gpiog {
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u-boot,dm-pre-reloc;
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};
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&gpioh {
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u-boot,dm-pre-reloc;
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};
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&gpioi {
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u-boot,dm-pre-reloc;
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};
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&gpioj {
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u-boot,dm-pre-reloc;
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};
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&gpiok {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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fmc_pins_d32: fmc_d32@0 {
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u-boot,dm-pre-reloc;
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pins
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{
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pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
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<STM32_PINMUX('I', 9, AF12)>, /* D30 */
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<STM32_PINMUX('I', 7, AF12)>, /* D29 */
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<STM32_PINMUX('I', 6, AF12)>, /* D28 */
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<STM32_PINMUX('I', 3, AF12)>, /* D27 */
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<STM32_PINMUX('I', 2, AF12)>, /* D26 */
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<STM32_PINMUX('I', 1, AF12)>, /* D25 */
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<STM32_PINMUX('I', 0, AF12)>, /* D24 */
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<STM32_PINMUX('H',15, AF12)>, /* D23 */
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<STM32_PINMUX('H',14, AF12)>, /* D22 */
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<STM32_PINMUX('H',13, AF12)>, /* D21 */
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<STM32_PINMUX('H',12, AF12)>, /* D20 */
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<STM32_PINMUX('H',11, AF12)>, /* D19 */
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<STM32_PINMUX('H',10, AF12)>, /* D18 */
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<STM32_PINMUX('H', 9, AF12)>, /* D17 */
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<STM32_PINMUX('H', 8, AF12)>, /* D16 */
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<STM32_PINMUX('D',10, AF12)>, /* D15 */
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<STM32_PINMUX('D', 9, AF12)>, /* D14 */
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<STM32_PINMUX('D', 8, AF12)>, /* D13 */
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<STM32_PINMUX('E',15, AF12)>, /* D12 */
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<STM32_PINMUX('E',14, AF12)>, /* D11 */
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<STM32_PINMUX('E',13, AF12)>, /* D10 */
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<STM32_PINMUX('E',12, AF12)>, /* D09 */
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<STM32_PINMUX('E',11, AF12)>, /* D08 */
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<STM32_PINMUX('E',10, AF12)>, /* D07 */
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<STM32_PINMUX('E', 9, AF12)>, /* D06 */
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<STM32_PINMUX('E', 8, AF12)>, /* D05 */
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<STM32_PINMUX('E', 7, AF12)>, /* D04 */
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<STM32_PINMUX('D', 1, AF12)>, /* D03 */
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<STM32_PINMUX('D', 0, AF12)>, /* D02 */
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<STM32_PINMUX('D',15, AF12)>, /* D01 */
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<STM32_PINMUX('D',14, AF12)>, /* D00 */
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<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
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<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
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<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
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<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
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<STM32_PINMUX('G', 5, AF12)>, /* BA1 */
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<STM32_PINMUX('G', 4, AF12)>, /* BA0 */
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<STM32_PINMUX('G', 1, AF12)>, /* A11 */
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<STM32_PINMUX('G', 0, AF12)>, /* A10 */
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<STM32_PINMUX('F',15, AF12)>, /* A09 */
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<STM32_PINMUX('F',14, AF12)>, /* A08 */
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<STM32_PINMUX('F',13, AF12)>, /* A07 */
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<STM32_PINMUX('F',12, AF12)>, /* A06 */
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<STM32_PINMUX('F', 5, AF12)>, /* A05 */
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<STM32_PINMUX('F', 4, AF12)>, /* A04 */
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<STM32_PINMUX('F', 3, AF12)>, /* A03 */
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<STM32_PINMUX('F', 2, AF12)>, /* A02 */
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<STM32_PINMUX('F', 1, AF12)>, /* A01 */
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<STM32_PINMUX('F', 0, AF12)>, /* A00 */
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<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
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<STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
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<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
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<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
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<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
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<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
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slew-rate = <2>;
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u-boot,dm-pre-reloc;
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};
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};
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qspi_pins: qspi@0 {
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pins {
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pinmux = <STM32_PINMUX('F',10, AF9)>, /* CLK */
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<STM32_PINMUX('B', 6, AF10)>, /* BK1_NCS */
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<STM32_PINMUX('F', 8, AF10)>, /* BK1_IO0 */
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<STM32_PINMUX('F', 9, AF10)>, /* BK1_IO1 */
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<STM32_PINMUX('F', 7, AF9)>, /* BK1_IO2 */
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<STM32_PINMUX('F', 6, AF9)>; /* BK1_IO3 */
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slew-rate = <2>;
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};
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};
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usart3_pins_a: usart3-0 {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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};
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};
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};
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&pwrcfg {
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u-boot,dm-pre-reloc;
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};
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&qspi {
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reg = <0xa0001000 0x1000>, <0x90000000 0x1000000>;
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flash0: n25q128a@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <108000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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};
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};
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&rcc {
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u-boot,dm-pre-reloc;
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};
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&syscfg {
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u-boot,dm-pre-reloc;
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};
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&timers5 {
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u-boot,dm-pre-reloc;
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};
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