Lars Povlsen 7048bb13b2 mips: vcoreiii: Fix cache coherency issues ... This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>		2020-04-09 18:55:59 +02:00
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mach	mips: vcoreiii: Fix cache coherency issues	2020-04-09 18:55:59 +02:00
ioremap.h	MSCC: add support for Ocelot SoCs	2018-12-19 15:23:01 +01:00