mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
b73e8bf453
Add TF-A FIP support for trusted boot on STM32MP15x, when STM32MP15x_STM32IMAGE is not activated. With FIP support the SSBL partition is named "fip" and its size is 4MB, so the ENV partition name in device tree (for SD card or eMMC) or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_REDUND) need to be modified. With FIP the TEE MTD partitions are removed because the OP-TEE binray are included in the FIP containers. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
224 lines
3.3 KiB
Text
224 lines
3.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
|
|
/*
|
|
* Copyright : STMicroelectronics 2018
|
|
*/
|
|
|
|
#include <dt-bindings/clock/stm32mp1-clksrc.h>
|
|
#include "stm32mp15-u-boot.dtsi"
|
|
#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
|
|
|
|
/ {
|
|
aliases {
|
|
i2c3 = &i2c4;
|
|
};
|
|
|
|
config {
|
|
u-boot,boot-led = "heartbeat";
|
|
u-boot,error-led = "error";
|
|
u-boot,mmc-env-partition = "fip";
|
|
st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
|
|
};
|
|
|
|
#ifdef CONFIG_STM32MP15x_STM32IMAGE
|
|
config {
|
|
u-boot,mmc-env-partition = "ssbl";
|
|
};
|
|
|
|
/* only needed for boot with TF-A, witout FIP support */
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
|
|
reserved-memory {
|
|
optee@fe000000 {
|
|
reg = <0xfe000000 0x02000000>;
|
|
no-map;
|
|
};
|
|
};
|
|
#endif
|
|
|
|
led {
|
|
red {
|
|
label = "error";
|
|
gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
|
|
default-state = "off";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
&clk_hse {
|
|
st,digbypass;
|
|
};
|
|
|
|
&i2c4 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&i2c4_pins_a {
|
|
u-boot,dm-pre-reloc;
|
|
pins {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
&pmic {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&rcc {
|
|
st,clksrc = <
|
|
CLK_MPU_PLL1P
|
|
CLK_AXI_PLL2P
|
|
CLK_MCU_PLL3P
|
|
CLK_PLL12_HSE
|
|
CLK_PLL3_HSE
|
|
CLK_PLL4_HSE
|
|
CLK_RTC_LSE
|
|
CLK_MCO1_DISABLED
|
|
CLK_MCO2_DISABLED
|
|
>;
|
|
|
|
st,clkdiv = <
|
|
1 /*MPU*/
|
|
0 /*AXI*/
|
|
0 /*MCU*/
|
|
1 /*APB1*/
|
|
1 /*APB2*/
|
|
1 /*APB3*/
|
|
1 /*APB4*/
|
|
2 /*APB5*/
|
|
23 /*RTC*/
|
|
0 /*MCO1*/
|
|
0 /*MCO2*/
|
|
>;
|
|
|
|
st,pkcs = <
|
|
CLK_CKPER_HSE
|
|
CLK_FMC_ACLK
|
|
CLK_QSPI_ACLK
|
|
CLK_ETH_DISABLED
|
|
CLK_SDMMC12_PLL4P
|
|
CLK_DSI_DSIPLL
|
|
CLK_STGEN_HSE
|
|
CLK_USBPHY_HSE
|
|
CLK_SPI2S1_PLL3Q
|
|
CLK_SPI2S23_PLL3Q
|
|
CLK_SPI45_HSI
|
|
CLK_SPI6_HSI
|
|
CLK_I2C46_HSI
|
|
CLK_SDMMC3_PLL4P
|
|
CLK_USBO_USBPHY
|
|
CLK_ADC_CKPER
|
|
CLK_CEC_LSE
|
|
CLK_I2C12_HSI
|
|
CLK_I2C35_HSI
|
|
CLK_UART1_HSI
|
|
CLK_UART24_HSI
|
|
CLK_UART35_HSI
|
|
CLK_UART6_HSI
|
|
CLK_UART78_HSI
|
|
CLK_SPDIF_PLL4P
|
|
CLK_FDCAN_PLL4R
|
|
CLK_SAI1_PLL3Q
|
|
CLK_SAI2_PLL3Q
|
|
CLK_SAI3_PLL3Q
|
|
CLK_SAI4_PLL3Q
|
|
CLK_RNG1_LSI
|
|
CLK_RNG2_LSI
|
|
CLK_LPTIM1_PCLK1
|
|
CLK_LPTIM23_PCLK3
|
|
CLK_LPTIM45_LSE
|
|
>;
|
|
|
|
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
|
pll2: st,pll@1 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <1>;
|
|
cfg = < 2 65 1 0 0 PQR(1,1,1) >;
|
|
frac = < 0x1400 >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
|
pll3: st,pll@2 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <2>;
|
|
cfg = < 1 33 1 16 36 PQR(1,1,1) >;
|
|
frac = < 0x1a04 >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
|
pll4: st,pll@3 {
|
|
compatible = "st,stm32mp1-pll";
|
|
reg = <3>;
|
|
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
&sdmmc1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&sdmmc1_b4_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc1_dir_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
|
|
&sdmmc2_b4_pins_a {
|
|
u-boot,dm-spl;
|
|
pins1 {
|
|
u-boot,dm-spl;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&sdmmc2_d47_pins_a {
|
|
u-boot,dm-spl;
|
|
pins {
|
|
u-boot,dm-spl;
|
|
};
|
|
};
|
|
|
|
&uart4 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&uart4_pins_a {
|
|
u-boot,dm-pre-reloc;
|
|
pins1 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-pre-reloc;
|
|
/* pull-up on rx to avoid floating level */
|
|
bias-pull-up;
|
|
};
|
|
};
|