mirror of
https://github.com/AsahiLinux/u-boot
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93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard (void)
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{
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puts ("Board: Freescale M5282EVB Evaluation Board\n");
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return 0;
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}
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long int initdram (int board_type)
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{
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u32 dramsize, i, dramclk;
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dramsize = CFG_SDRAM_SIZE * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
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{
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dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
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/* Initialize DRAM Control Register: DCR */
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MCFSDRAMC_DCR = (0
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| MCFSDRAMC_DCR_RTIM_6
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| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
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/* Initialize DACR0 */
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MCFSDRAMC_DACR0 = (0
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| MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
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| MCFSDRAMC_DACR_CASL(1)
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| MCFSDRAMC_DACR_CBM(3)
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| MCFSDRAMC_DACR_PS_32);
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/* Initialize DMR0 */
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MCFSDRAMC_DMR0 = (0
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| ((dramsize - 1) & 0xFFFC0000)
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| MCFSDRAMC_DMR_V);
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/* Set IP (bit 3) in DACR */
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
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/* Wait 30ns to allow banks to precharge */
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for (i = 0; i < 5; i++) {
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asm ("nop");
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}
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/* Write to this block to initiate precharge */
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*(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
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/* Set RE (bit 15) in DACR */
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
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/* Wait for at least 8 auto refresh cycles to occur */
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for (i = 0; i < 2000; i++) {
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asm(" nop");
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}
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/* Finish the configuration by issuing the IMRS. */
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
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/* Write to the SDRAM Mode Register */
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*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
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}
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return dramsize;
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}
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