mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
d8d33b6d4d
Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
39 lines
638 B
Text
39 lines
638 B
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx6ull.dtsi"
|
|
#include "imx6ull-dart-6ul.dtsi"
|
|
|
|
/ {
|
|
model = "Variscite DART-6UL Evaluation Kit";
|
|
compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
|
|
};
|
|
|
|
&usdhc2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
|
dr_mode = "otg";
|
|
srp-disable;
|
|
hnp-disable;
|
|
adp-disable;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl_usb_otg1_id: usbotg1idgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
};
|