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d3c56e2a82
There are three different divider values in the DIV_CTRL register
controlled by the k3-pll driver. Currently the ti_pll_clk_set_rate
function writes the entire register when programming plld, even though
plld only resides in the lower 6 bits.
Change the plld programming to read-modify-write to only affect the
relevant bits for plld and to preserve the other two divider values
present in the upper 16 bits, otherwise they will always get set to zero
when programming plld.
Fixes: 0aa2930ca1
("clk: add support for TI K3 SoC PLL")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
292 lines
6.7 KiB
C
292 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Texas Instruments K3 SoC PLL clock driver
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
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* Tero Kristo <t-kristo@ti.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <div64.h>
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#include <errno.h>
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#include <clk-uclass.h>
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#include <linux/clk-provider.h>
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#include "k3-clk.h"
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#include <linux/rational.h>
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/* 16FFT register offsets */
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#define PLL_16FFT_CFG 0x08
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#define PLL_KICK0 0x10
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#define PLL_KICK1 0x14
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#define PLL_16FFT_CTRL 0x20
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#define PLL_16FFT_STAT 0x24
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#define PLL_16FFT_FREQ_CTRL0 0x30
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#define PLL_16FFT_FREQ_CTRL1 0x34
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#define PLL_16FFT_DIV_CTRL 0x38
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/* CTRL register bits */
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#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
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#define PLL_16FFT_CTRL_PLL_EN BIT(15)
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#define PLL_16FFT_CTRL_DSM_EN BIT(1)
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/* STAT register bits */
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#define PLL_16FFT_STAT_LOCK BIT(0)
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/* FREQ_CTRL0 bits */
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#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff
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/* DIV CTRL register bits */
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#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
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#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
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#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
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/* KICK register magic values */
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#define PLL_KICK0_VALUE 0x68ef3490
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#define PLL_KICK1_VALUE 0xd172bc5a
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/**
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* struct ti_pll_clk - TI PLL clock data info structure
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* @clk: core clock structure
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* @reg: memory address of the PLL controller
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*/
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struct ti_pll_clk {
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struct clk clk;
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void __iomem *reg;
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};
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#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
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static int ti_pll_wait_for_lock(struct clk *clk)
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{
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struct ti_pll_clk *pll = to_clk_pll(clk);
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u32 stat;
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int i;
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for (i = 0; i < 100000; i++) {
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stat = readl(pll->reg + PLL_16FFT_STAT);
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if (stat & PLL_16FFT_STAT_LOCK)
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return 0;
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}
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printf("%s: pll (%s) failed to lock\n", __func__,
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clk->dev->name);
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return -EBUSY;
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}
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static ulong ti_pll_clk_get_rate(struct clk *clk)
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{
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struct ti_pll_clk *pll = to_clk_pll(clk);
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u64 current_freq;
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u64 parent_freq = clk_get_parent_rate(clk);
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u32 pllm;
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u32 plld;
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u32 pllfm;
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u32 ctrl;
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/* Check if we are in bypass */
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ctrl = readl(pll->reg + PLL_16FFT_CTRL);
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if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
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return parent_freq;
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pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
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pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
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plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
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PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
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current_freq = parent_freq * pllm / plld;
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if (pllfm) {
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u64 tmp;
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tmp = parent_freq * pllfm;
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do_div(tmp, plld);
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tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
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current_freq += tmp;
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}
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return current_freq;
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}
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static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct ti_pll_clk *pll = to_clk_pll(clk);
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u64 current_freq;
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u64 parent_freq = clk_get_parent_rate(clk);
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int ret;
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u32 ctrl;
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unsigned long pllm;
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u32 pllfm = 0;
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unsigned long plld;
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u32 div_ctrl;
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u32 rem;
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int shift;
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debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate);
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if (ti_pll_clk_get_rate(clk) == rate)
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return rate;
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if (rate != parent_freq)
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/*
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* Attempt with higher max multiplier value first to give
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* some space for fractional divider to kick in.
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*/
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for (shift = 8; shift >= 0; shift -= 8) {
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rational_best_approximation(rate, parent_freq,
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((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
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PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
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if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
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break;
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}
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/* Put PLL to bypass mode */
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ctrl = readl(pll->reg + PLL_16FFT_CTRL);
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ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
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writel(ctrl, pll->reg + PLL_16FFT_CTRL);
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if (rate == parent_freq) {
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debug("%s: put %s to bypass\n", __func__, clk->dev->name);
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return rate;
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}
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debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
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__func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
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/* Check if we need fractional config */
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if (plld > 1) {
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pllfm = pllm % plld;
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pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
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rem = pllfm % plld;
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pllfm /= plld;
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if (rem)
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pllfm++;
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pllm /= plld;
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plld = 1;
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}
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if (pllfm)
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ctrl |= PLL_16FFT_CTRL_DSM_EN;
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else
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ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
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writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
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writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
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/*
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* div_ctrl register contains other divider values, so rmw
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* only plld and leave existing values alone
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*/
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div_ctrl = readl(pll->reg + PLL_16FFT_DIV_CTRL);
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div_ctrl &= ~PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
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div_ctrl |= plld;
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writel(div_ctrl, pll->reg + PLL_16FFT_DIV_CTRL);
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ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
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ctrl |= PLL_16FFT_CTRL_PLL_EN;
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writel(ctrl, pll->reg + PLL_16FFT_CTRL);
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ret = ti_pll_wait_for_lock(clk);
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if (ret)
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return ret;
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debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
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__func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
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current_freq = parent_freq * pllm / plld;
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if (pllfm) {
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u64 tmp;
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tmp = parent_freq * pllfm;
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do_div(tmp, plld);
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tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
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current_freq += tmp;
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}
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return current_freq;
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}
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static int ti_pll_clk_enable(struct clk *clk)
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{
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struct ti_pll_clk *pll = to_clk_pll(clk);
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u32 ctrl;
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ctrl = readl(pll->reg + PLL_16FFT_CTRL);
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ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
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ctrl |= PLL_16FFT_CTRL_PLL_EN;
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writel(ctrl, pll->reg + PLL_16FFT_CTRL);
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return ti_pll_wait_for_lock(clk);
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}
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static int ti_pll_clk_disable(struct clk *clk)
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{
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struct ti_pll_clk *pll = to_clk_pll(clk);
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u32 ctrl;
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ctrl = readl(pll->reg + PLL_16FFT_CTRL);
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ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
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writel(ctrl, pll->reg + PLL_16FFT_CTRL);
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return 0;
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}
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static const struct clk_ops ti_pll_clk_ops = {
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.get_rate = ti_pll_clk_get_rate,
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.set_rate = ti_pll_clk_set_rate,
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.enable = ti_pll_clk_enable,
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.disable = ti_pll_clk_disable,
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};
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struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
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void __iomem *reg)
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{
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struct ti_pll_clk *pll;
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int ret;
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int i;
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u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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pll->reg = reg;
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ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
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if (ret) {
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printf("%s: failed to register: %d\n", __func__, ret);
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kfree(pll);
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return ERR_PTR(ret);
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}
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/* Unlock the PLL registers */
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writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
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writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
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/* Enable all HSDIV outputs */
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cfg = readl(pll->reg + PLL_16FFT_CFG);
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for (i = 0; i < 16; i++) {
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hsdiv_presence_bit = BIT(16 + i);
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hsdiv_ctrl_offs = 0x80 + (i * 4);
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/* Enable HSDIV output if present */
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if ((hsdiv_presence_bit & cfg) != 0UL) {
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ctrl = readl(pll->reg + hsdiv_ctrl_offs);
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ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
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writel(ctrl, pll->reg + hsdiv_ctrl_offs);
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}
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}
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return &pll->clk;
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}
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U_BOOT_DRIVER(ti_pll_clk) = {
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.name = "ti-pll-clk",
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.id = UCLASS_CLK,
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.ops = &ti_pll_clk_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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