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https://github.com/AsahiLinux/u-boot
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39f633320c
Tegra186's MMC controller needs to be explicitly identified. Add another compatible value for it. Tegra186 will use an entirely different clock/reset control mechanism to existing chips, and will use standard clock/reset APIs rather than the existing Tegra-specific custom APIs. The driver support for that isn't ready yet, so simply disable all clock/reset usage if compiling for Tegra186. This must happen at compile time rather than run-time since the custom APIs won't even be compiled in on Tegra186. In the long term, the plan would be to convert the existing custom APIs to standard APIs and get rid of the ifdefs completely. The system's main eMMC will work without any clock/reset support, since the firmware will have already initialized the controller in order to load U-Boot. Hence the driver is useful even in this apparently crippled state. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
151 lines
6.2 KiB
C
151 lines
6.2 KiB
C
/*
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* (C) Copyright 2009 SAMSUNG Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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* Portions Copyright (C) 2011-2012 NVIDIA Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TEGRA_MMC_H_
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#define __TEGRA_MMC_H_
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#include <fdtdec.h>
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#include <asm/gpio.h>
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/* for mmc_config definition */
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#include <mmc.h>
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#ifndef __ASSEMBLY__
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struct tegra_mmc {
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unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
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unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
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unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
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unsigned int argument; /* _ARGUMENT_0 */
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unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */
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unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */
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unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
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unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
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unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
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unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
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unsigned int bdata; /* _BUFFER_DATA_PORT_0 */
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unsigned int prnsts; /* _PRESENT_STATE_0 */
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unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */
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unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */
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unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */
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unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */
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unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */
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unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */
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unsigned char swrst; /* _SW_RESET_ 31:24 */
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unsigned int norintsts; /* _INTERRUPT_STATUS_0 */
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unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */
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unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */
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unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
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unsigned char res1[2]; /* _RESERVED 31:16 */
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unsigned int capareg; /* _CAPABILITIES_0 */
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unsigned char res2[4]; /* RESERVED, offset 44h-47h */
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unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */
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unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */
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unsigned short setacmd12err; /* offset 50h */
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unsigned short setinterr; /* offset 52h */
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unsigned char admaerr; /* offset 54h */
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unsigned char res4[3]; /* RESERVED, offset 55h-57h */
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unsigned long admaaddr; /* offset 58h-5Fh */
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unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */
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unsigned short slotintstatus; /* offset FCh */
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unsigned short hcver; /* HOST Version */
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unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */
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unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */
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unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */
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unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */
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unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */
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unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
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unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
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unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
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unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */
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unsigned int res6[47]; /* 0x124 ~ 0x1DC */
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unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */
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unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */
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unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */
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unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */
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};
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#define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0)
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1)
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1)
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1)
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#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
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#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
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#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
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#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
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#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
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#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
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#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
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#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
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#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
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#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
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#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
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#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
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#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
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#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
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#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
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#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
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#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
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#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
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#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
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#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
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#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
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#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
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#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
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#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
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#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
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#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
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#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
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#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
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#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
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#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
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#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
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#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
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#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
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/* SDMMC1/3 settings from section 24.6 of T30 TRM */
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#define MEMCOMP_PADCTRL_VREF 7
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#define AUTO_CAL_ENABLED (1 << 29)
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#define AUTO_CAL_PD_OFFSET (0x70 << 8)
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#define AUTO_CAL_PU_OFFSET (0x62 << 0)
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struct mmc_host {
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struct tegra_mmc *reg;
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int id; /* device id/number, 0-3 */
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int enabled; /* 1 to enable, 0 to disable */
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int width; /* Bus Width, 1, 4 or 8 */
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#ifndef CONFIG_TEGRA186
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enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
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#endif
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struct gpio_desc cd_gpio; /* Change Detect GPIO */
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struct gpio_desc pwr_gpio; /* Power GPIO */
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struct gpio_desc wp_gpio; /* Write Protect GPIO */
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unsigned int version; /* SDHCI spec. version */
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unsigned int clock; /* Current clock (MHz) */
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struct mmc_config cfg; /* mmc configuration */
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};
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void pad_init_mmc(struct mmc_host *host);
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#endif /* __ASSEMBLY__ */
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#endif /* __TEGRA_MMC_H_ */
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