mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-10-23 14:34:49 +00:00
abddcd52ab
So far there are two copies of Azalia struct defines with one in baytrail and the other one in braswell. This consolidates these two into one, put it in the common place, and remove the prefix pch_ to these structs to make their names more generic. This also corrects reset_wait_timer from us to ms. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
146 lines
5 KiB
C
146 lines
5 KiB
C
/*
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* Copyright (C) 2015, Intel Corporation
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* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: Intel
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*/
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#ifndef __FSP_VPD_H__
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#define __FSP_VPD_H__
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struct __packed memory_upd {
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u64 signature; /* Offset 0x0020 */
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u8 revision; /* Offset 0x0028 */
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u8 unused2[7]; /* Offset 0x0029 */
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u16 mrc_init_tseg_size; /* Offset 0x0030 */
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u16 mrc_init_mmio_size; /* Offset 0x0032 */
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u8 mrc_init_spd_addr1; /* Offset 0x0034 */
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u8 mrc_init_spd_addr2; /* Offset 0x0035 */
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u8 mem_ch0_config; /* Offset 0x0036 */
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u8 mem_ch1_config; /* Offset 0x0037 */
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u32 memory_spd_ptr; /* Offset 0x0038 */
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u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */
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u8 aperture_size; /* Offset 0x003d */
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u8 gtt_size; /* Offset 0x003e */
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u8 legacy_seg_decode; /* Offset 0x003f */
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u8 enable_dvfs; /* Offset 0x0040 */
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u8 memory_type; /* Offset 0x0041 */
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u8 enable_ca_mirror; /* Offset 0x0042 */
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u8 reserved[189]; /* Offset 0x0043 */
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};
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struct gpio_family {
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u32 confg;
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u32 confg_changes;
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u32 misc;
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u32 mmio_addr;
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wchar_t *name;
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};
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struct gpio_pad {
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u32 confg0;
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u32 confg0_changes;
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u32 confg1;
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u32 confg1_changes;
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u32 community;
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u32 mmio_addr;
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wchar_t *name;
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u32 misc;
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};
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struct __packed silicon_upd {
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u64 signature; /* Offset 0x0100 */
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u8 revision; /* Offset 0x0108 */
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u8 unused3[7]; /* Offset 0x0109 */
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u8 sdcard_mode; /* Offset 0x0110 */
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u8 enable_hsuart0; /* Offset 0x0111 */
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u8 enable_hsuart1; /* Offset 0x0112 */
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u8 enable_azalia; /* Offset 0x0113 */
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struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */
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u8 enable_sata; /* Offset 0x0118 */
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u8 enable_xhci; /* Offset 0x0119 */
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u8 lpe_mode; /* Offset 0x011a */
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u8 enable_dma0; /* Offset 0x011b */
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u8 enable_dma1; /* Offset 0x011c */
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u8 enable_i2c0; /* Offset 0x011d */
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u8 enable_i2c1; /* Offset 0x011e */
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u8 enable_i2c2; /* Offset 0x011f */
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u8 enable_i2c3; /* Offset 0x0120 */
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u8 enable_i2c4; /* Offset 0x0121 */
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u8 enable_i2c5; /* Offset 0x0122 */
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u8 enable_i2c6; /* Offset 0x0123 */
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u32 graphics_config_ptr; /* Offset 0x0124 */
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struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */
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struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */
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u8 disable_punit_pwr_config; /* Offset 0x0130 */
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u8 chv_svid_config; /* Offset 0x0131 */
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u8 disable_dptf; /* Offset 0x0132 */
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u8 emmc_mode; /* Offset 0x0133 */
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u8 usb3_clk_ssc; /* Offset 0x0134 */
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u8 disp_clk_ssc; /* Offset 0x0135 */
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u8 sata_clk_ssc; /* Offset 0x0136 */
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u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */
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u8 usb2_port0_txi_set; /* Offset 0x0138 */
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u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */
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u8 usb2_port0_tx_pe_half; /* Offset 0x013a */
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u8 usb2_port1_pe_txi_set; /* Offset 0x013b */
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u8 usb2_port1_txi_set; /* Offset 0x013c */
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u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */
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u8 usb2_port1_tx_pe_half; /* Offset 0x013e */
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u8 usb2_port2_pe_txi_set; /* Offset 0x013f */
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u8 usb2_port2_txi_set; /* Offset 0x0140 */
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u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */
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u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */
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u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */
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u8 usb2_port3_txi_set; /* Offset 0x0144 */
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u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */
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u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */
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u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */
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u8 usb2_port4_txi_set; /* Offset 0x0148 */
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u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */
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u8 usb2_port4_tx_pe_half; /* Offset 0x014a */
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u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */
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u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */
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u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */
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u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */
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u8 sata_speed; /* Offset 0x014f */
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u8 usb_ssic_port; /* Offset 0x0150 */
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u8 usb_hsic_port; /* Offset 0x0151 */
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u8 pcie_rootport_speed; /* Offset 0x0152 */
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u8 enable_ssic; /* Offset 0x0153 */
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u32 logo_ptr; /* Offset 0x0154 */
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u32 logo_size; /* Offset 0x0158 */
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u8 rtc_lock; /* Offset 0x015c */
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u8 pmic_i2c_bus; /* Offset 0x015d */
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u8 enable_isp; /* Offset 0x015e */
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u8 isp_pci_dev_config; /* Offset 0x015f */
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u8 turbo_mode; /* Offset 0x0160 */
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u8 pnp_settings; /* Offset 0x0161 */
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u8 sd_detect_chk; /* Offset 0x0162 */
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u8 reserved[411]; /* Offset 0x0163 */
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};
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#define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */
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#define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */
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struct __packed upd_region {
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u64 signature; /* Offset 0x0000 */
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u8 revision; /* Offset 0x0008 */
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u8 unused0[7]; /* Offset 0x0009 */
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u32 memory_upd_offset; /* Offset 0x0010 */
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u32 silicon_upd_offset; /* Offset 0x0014 */
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u64 unused1; /* Offset 0x0018 */
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struct memory_upd memory_upd; /* Offset 0x0020 */
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struct silicon_upd silicon_upd; /* Offset 0x0100 */
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u16 terminator; /* Offset 0x02fe */
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};
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#define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */
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struct __packed vpd_region {
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u64 sign; /* Offset 0x0000 */
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u32 img_rev; /* Offset 0x0008 */
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u32 upd_offset; /* Offset 0x000c */
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};
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#endif /* __FSP_VPD_H__ */
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