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70ad375ee4
This renames all the Tegra20 pinmux pins and functions so they have a prefix which matches the type name. The entries in tegra20_pingroups[] are all updated to remove the columns which are no longer used. All affected code is updated to match. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
425 lines
11 KiB
C
425 lines
11 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra20 pin multiplexing functions */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/pinmux.h>
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/*
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* This defines the order of the pin mux control bits in the registers. For
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* some reason there is no correspendence between the tristate, pin mux and
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* pullup/pulldown registers.
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*/
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enum pmux_ctlid {
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/* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
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MUXCTL_UAA,
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MUXCTL_UAB,
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MUXCTL_UAC,
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MUXCTL_UAD,
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MUXCTL_UDA,
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MUXCTL_RESERVED5,
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MUXCTL_ATE,
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MUXCTL_RM,
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MUXCTL_ATB,
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MUXCTL_RESERVED9,
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MUXCTL_ATD,
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MUXCTL_ATC,
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MUXCTL_ATA,
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MUXCTL_KBCF,
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MUXCTL_KBCE,
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MUXCTL_SDMMC1,
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/* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
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MUXCTL_GMA,
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MUXCTL_GMC,
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MUXCTL_HDINT,
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MUXCTL_SLXA,
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MUXCTL_OWC,
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MUXCTL_SLXC,
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MUXCTL_SLXD,
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MUXCTL_SLXK,
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MUXCTL_UCA,
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MUXCTL_UCB,
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MUXCTL_DTA,
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MUXCTL_DTB,
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MUXCTL_RESERVED28,
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MUXCTL_DTC,
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MUXCTL_DTD,
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MUXCTL_DTE,
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/* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
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MUXCTL_DDC,
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MUXCTL_CDEV1,
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MUXCTL_CDEV2,
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MUXCTL_CSUS,
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MUXCTL_I2CP,
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MUXCTL_KBCA,
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MUXCTL_KBCB,
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MUXCTL_KBCC,
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MUXCTL_IRTX,
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MUXCTL_IRRX,
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MUXCTL_DAP1,
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MUXCTL_DAP2,
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MUXCTL_DAP3,
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MUXCTL_DAP4,
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MUXCTL_GMB,
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MUXCTL_GMD,
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/* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
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MUXCTL_GME,
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MUXCTL_GPV,
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MUXCTL_GPU,
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MUXCTL_SPDO,
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MUXCTL_SPDI,
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MUXCTL_SDB,
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MUXCTL_SDC,
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MUXCTL_SDD,
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MUXCTL_SPIH,
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MUXCTL_SPIG,
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MUXCTL_SPIF,
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MUXCTL_SPIE,
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MUXCTL_SPID,
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MUXCTL_SPIC,
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MUXCTL_SPIB,
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MUXCTL_SPIA,
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/* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
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MUXCTL_LPW0,
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MUXCTL_LPW1,
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MUXCTL_LPW2,
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MUXCTL_LSDI,
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MUXCTL_LSDA,
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MUXCTL_LSPI,
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MUXCTL_LCSN,
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MUXCTL_LDC,
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MUXCTL_LSCK,
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MUXCTL_LSC0,
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MUXCTL_LSC1,
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MUXCTL_LHS,
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MUXCTL_LVS,
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MUXCTL_LM0,
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MUXCTL_LM1,
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MUXCTL_LVP0,
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/* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
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MUXCTL_LD0,
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MUXCTL_LD1,
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MUXCTL_LD2,
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MUXCTL_LD3,
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MUXCTL_LD4,
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MUXCTL_LD5,
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MUXCTL_LD6,
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MUXCTL_LD7,
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MUXCTL_LD8,
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MUXCTL_LD9,
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MUXCTL_LD10,
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MUXCTL_LD11,
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MUXCTL_LD12,
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MUXCTL_LD13,
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MUXCTL_LD14,
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MUXCTL_LD15,
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/* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
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MUXCTL_LD16,
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MUXCTL_LD17,
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MUXCTL_LHP1,
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MUXCTL_LHP2,
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MUXCTL_LVP1,
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MUXCTL_LHP0,
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MUXCTL_RESERVED102,
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MUXCTL_LPP,
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MUXCTL_LDI,
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MUXCTL_PMC,
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MUXCTL_CRTP,
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MUXCTL_PTA,
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MUXCTL_RESERVED108,
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MUXCTL_KBCD,
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MUXCTL_GPU7,
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MUXCTL_DTF,
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MUXCTL_NONE = -1,
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};
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/*
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* And this defines the order of the pullup/pulldown controls which are again
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* in a different order
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*/
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enum pmux_pullid {
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/* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
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PUCTL_ATA,
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PUCTL_ATB,
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PUCTL_ATC,
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PUCTL_ATD,
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PUCTL_ATE,
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PUCTL_DAP1,
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PUCTL_DAP2,
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PUCTL_DAP3,
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PUCTL_DAP4,
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PUCTL_DTA,
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PUCTL_DTB,
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PUCTL_DTC,
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PUCTL_DTD,
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PUCTL_DTE,
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PUCTL_DTF,
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PUCTL_GPV,
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/* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
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PUCTL_RM,
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PUCTL_I2CP,
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PUCTL_PTA,
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PUCTL_GPU7,
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PUCTL_KBCA,
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PUCTL_KBCB,
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PUCTL_KBCC,
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PUCTL_KBCD,
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PUCTL_SPDI,
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PUCTL_SPDO,
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PUCTL_GPSLXAU,
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PUCTL_CRTP,
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PUCTL_SLXC,
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PUCTL_SLXD,
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PUCTL_SLXK,
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/* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
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PUCTL_CDEV1,
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PUCTL_CDEV2,
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PUCTL_SPIA,
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PUCTL_SPIB,
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PUCTL_SPIC,
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PUCTL_SPID,
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PUCTL_SPIE,
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PUCTL_SPIF,
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PUCTL_SPIG,
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PUCTL_SPIH,
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PUCTL_IRTX,
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PUCTL_IRRX,
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PUCTL_GME,
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PUCTL_RESERVED45,
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PUCTL_XM2D,
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PUCTL_XM2C,
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/* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
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PUCTL_UAA,
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PUCTL_UAB,
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PUCTL_UAC,
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PUCTL_UAD,
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PUCTL_UCA,
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PUCTL_UCB,
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PUCTL_LD17,
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PUCTL_LD19_18,
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PUCTL_LD21_20,
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PUCTL_LD23_22,
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PUCTL_LS,
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PUCTL_LC,
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PUCTL_CSUS,
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PUCTL_DDRC,
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PUCTL_SDC,
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PUCTL_SDD,
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/* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
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PUCTL_KBCF,
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PUCTL_KBCE,
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PUCTL_PMCA,
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PUCTL_PMCB,
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PUCTL_PMCC,
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PUCTL_PMCD,
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PUCTL_PMCE,
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PUCTL_CK32,
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PUCTL_UDA,
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PUCTL_SDMMC1,
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PUCTL_GMA,
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PUCTL_GMB,
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PUCTL_GMC,
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PUCTL_GMD,
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PUCTL_DDC,
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PUCTL_OWC,
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PUCTL_NONE = -1
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};
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/* Convenient macro for defining pin group properties */
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#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
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{ \
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.funcs = { \
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PMUX_FUNC_ ## f0, \
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PMUX_FUNC_ ## f1, \
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PMUX_FUNC_ ## f2, \
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PMUX_FUNC_ ## f3, \
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}, \
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.ctl_id = mux, \
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.pull_id = pupd \
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}
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/* A normal pin group where the mux name and pull-up name match */
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#define PIN(pingrp, f0, f1, f2, f3) \
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PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
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/* A pin group where the pull-up name doesn't have a 1-1 mapping */
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#define PINP(pingrp, f0, f1, f2, f3, pupd) \
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PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
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/* A pin group number which is not used */
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#define PIN_RESERVED \
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PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
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#define DRVGRP(drvgrp) \
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PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
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static const struct pmux_pingrp_desc tegra20_pingroups[] = {
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PIN(ATA, IDE, NAND, GMI, RSVD4),
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PIN(ATB, IDE, NAND, GMI, SDIO4),
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PIN(ATC, IDE, NAND, GMI, SDIO4),
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PIN(ATD, IDE, NAND, GMI, SDIO4),
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PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
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PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
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PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
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PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
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PIN(DAP2, DAP2, TWC, RSVD3, GMI),
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PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
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PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
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PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
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PIN(DTB, RSVD1, RSVD2, VI, SPI1),
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PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
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PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
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PIN(DTE, RSVD1, RSVD2, VI, SPI1),
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PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
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PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
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PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
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PIN(IRTX, UARTA, UARTB, GMI, SPI4),
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PIN(IRRX, UARTA, UARTB, GMI, SPI4),
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PIN(KBCB, KBC, NAND, SDIO2, MIO),
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PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
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PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
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PIN(PTA, I2C2, HDMI, GMI, RSVD4),
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PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
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PIN(KBCE, KBC, NAND, OWR, RSVD4),
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PIN(KBCF, KBC, NAND, TRACE, MIO),
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PIN(GMA, UARTE, SPI3, GMI, SDIO4),
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PIN(GMC, UARTD, SPI4, GMI, SFLASH),
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PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
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PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
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PIN(GME, RSVD1, DAP5, GMI, SDIO4),
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PIN(SDC, PWM, TWC, SDIO3, SPI3),
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PIN(SDD, UARTA, PWM, SDIO3, SPI3),
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PIN_RESERVED,
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PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
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PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
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PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
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PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
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PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
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PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
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PIN(SPIA, SPI1, SPI2, SPI3, GMI),
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PIN(SPIB, SPI1, SPI2, SPI3, GMI),
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PIN(SPIC, SPI1, SPI2, SPI3, GMI),
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PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
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PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
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PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
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PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
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PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
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PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
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PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
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PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
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PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
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PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
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PIN(UCB, UARTC, PWM, GMI, RSVD4),
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PIN_RESERVED,
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PIN(ATE, IDE, NAND, GMI, RSVD4),
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PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
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PIN_RESERVED,
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PIN_RESERVED,
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PIN(GMB, IDE, NAND, GMI, GMI_INT),
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PIN(GMD, RSVD1, NAND, GMI, SFLASH),
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PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
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/* 64 */
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PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
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PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
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PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
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PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
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PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
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PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
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PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
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PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
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PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
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PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
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PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
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PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
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PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
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PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
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PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
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PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
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/* 96 */
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PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
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PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
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PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
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PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
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PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
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PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
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PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
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PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
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PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
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PIN_RESERVED,
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PIN(KBCD, KBC, NAND, SDIO2, MIO),
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PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
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PIN(DTF, I2C3, RSVD2, VI, RSVD4),
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PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
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PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
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PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
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/* these pin groups only have pullup and pull down control */
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DRVGRP(CK32),
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DRVGRP(DDRC),
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DRVGRP(PMCA),
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DRVGRP(PMCB),
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DRVGRP(PMCC),
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DRVGRP(PMCD),
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DRVGRP(PMCE),
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DRVGRP(XM2C),
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DRVGRP(XM2D),
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};
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const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;
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