mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-14 07:13:03 +00:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
1058 lines
27 KiB
C
1058 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2007-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Modified by Xianghua Xiao, X.Xiao@motorola.com
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <sata.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <fsl_errata.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_srio.h>
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#ifdef CONFIG_FSL_CORENET
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fsl_qbman.h>
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#endif
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#include <fsl_usb.h>
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#include <hwconfig.h>
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#include <linux/compiler.h>
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#include "mp.h"
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#ifdef CONFIG_CHAIN_OF_TRUST
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#include <fsl_validate.h>
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#endif
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#ifdef CONFIG_FSL_CAAM
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#include <fsl_sec.h>
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#endif
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#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
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#include <asm/fsl_pamu.h>
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#include <fsl_secboot_err.h>
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#endif
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#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#include <nand.h>
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#include <errno.h>
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#endif
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#ifndef CONFIG_ARCH_QEMU_E500
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#include <fsl_ddr.h>
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#endif
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#include "../../../../drivers/ata/fsl_sata.h"
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#ifdef CONFIG_U_QE
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#include <fsl_qe.h>
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#endif
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#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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/*
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* For deriving usb clock from 100MHz sysclk, reference divisor is set
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* to a value of 5, which gives an intermediate value 20(100/5). The
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* multiplication factor integer is set to 24, which when multiplied to
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* above intermediate value provides clock for usb ip.
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*/
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void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
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{
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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if (sysinfo.diff_sysclk == 1) {
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clrbits_be32(&usb_phy->pllprg[1],
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CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
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setbits_be32(&usb_phy->pllprg[1],
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CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
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CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
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CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
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{
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#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
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u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
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/* Increase Disconnect Threshold by 50mV */
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xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
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INC_DCNT_THRESHOLD_50MV;
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/* Enable programming of USB High speed Disconnect threshold */
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xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
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out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
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xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
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/* Increase Disconnect Threshold by 50mV */
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xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
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INC_DCNT_THRESHOLD_50MV;
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/* Enable programming of USB High speed Disconnect threshold */
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xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
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out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
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#else
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u32 temp = 0;
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u32 status = in_be32(&usb_phy->status1);
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u32 squelch_prog_rd_0_2 =
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(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
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& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
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u32 squelch_prog_rd_3_5 =
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(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
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& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
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setbits_be32(&usb_phy->config1,
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CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
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setbits_be32(&usb_phy->config2,
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CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
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temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
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out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
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temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
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out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
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#endif
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}
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#endif
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#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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extern void qe_init(uint qe_base);
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extern void qe_reset(void);
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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#ifdef CONFIG_CPM2
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void config_8560_ioports (volatile ccsr_cpm_t * cpm)
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{
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int portnum;
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for (portnum = 0; portnum < 4; portnum++) {
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uint pmsk = 0,
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ppar = 0,
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psor = 0,
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pdir = 0,
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podr = 0,
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pdat = 0;
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iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
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iop_conf_t *eiopc = iopc + 32;
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uint msk = 1;
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/*
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* NOTE:
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* index 0 refers to pin 31,
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* index 31 refers to pin 0
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*/
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while (iopc < eiopc) {
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if (iopc->conf) {
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pmsk |= msk;
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if (iopc->ppar)
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ppar |= msk;
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if (iopc->psor)
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psor |= msk;
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if (iopc->pdir)
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pdir |= msk;
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if (iopc->podr)
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podr |= msk;
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if (iopc->pdat)
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pdat |= msk;
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}
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msk <<= 1;
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iopc++;
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}
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if (pmsk != 0) {
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volatile ioport_t *iop = ioport_addr (cpm, portnum);
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uint tpmsk = ~pmsk;
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/*
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* the (somewhat confused) paragraph at the
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* bottom of page 35-5 warns that there might
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* be "unknown behaviour" when programming
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* PSORx and PDIRx, if PPARx = 1, so I
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* decided this meant I had to disable the
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* dedicated function first, and enable it
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* last.
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*/
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iop->ppar &= tpmsk;
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iop->psor = (iop->psor & tpmsk) | psor;
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iop->podr = (iop->podr & tpmsk) | podr;
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iop->pdat = (iop->pdat & tpmsk) | pdat;
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iop->pdir = (iop->pdir & tpmsk) | pdir;
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iop->ppar |= ppar;
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}
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}
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}
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#endif
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#ifdef CONFIG_SYS_FSL_CPC
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#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
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void disable_cpc_sram(void)
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{
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int i;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
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/* find and disable LAW of SRAM */
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struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
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if (law.index == -1) {
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printf("\nFatal error happened\n");
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return;
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}
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disable_law(law.index);
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clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
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out_be32(&cpc->cpccsr0, 0);
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out_be32(&cpc->cpcsrcr0, 0);
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}
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}
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}
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#endif
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#if defined(T1040_TDM_QUIRK_CCSR_BASE)
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#ifdef CONFIG_POST
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#error POST memory test cannot be enabled with TDM
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#endif
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static void enable_tdm_law(void)
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{
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int ret;
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char buffer[HWCONFIG_BUFFER_SIZE] = {0};
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int tdm_hwconfig_enabled = 0;
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/*
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* Extract hwconfig from environment since environment
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* is not setup properly yet. Search for tdm entry in
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* hwconfig.
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*/
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ret = env_get_f("hwconfig", buffer, sizeof(buffer));
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if (ret > 0) {
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tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
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/* If tdm is defined in hwconfig, set law for tdm workaround */
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if (tdm_hwconfig_enabled)
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set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
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LAW_TRGT_IF_CCSR);
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}
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}
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#endif
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void enable_cpc(void)
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{
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int i;
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int ret;
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u32 size = 0;
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u32 cpccfg0;
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char buffer[HWCONFIG_BUFFER_SIZE];
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char cpc_subarg[16];
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bool have_hwconfig = false;
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int cpc_args = 0;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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/* Extract hwconfig from environment */
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ret = env_get_f("hwconfig", buffer, sizeof(buffer));
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if (ret > 0) {
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/*
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* If "en_cpc" is not defined in hwconfig then by default all
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* cpcs are enable. If this config is defined then individual
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* cpcs which have to be enabled should also be defined.
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* e.g en_cpc:cpc1,cpc2;
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*/
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if (hwconfig_f("en_cpc", buffer))
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have_hwconfig = true;
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}
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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if (have_hwconfig) {
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sprintf(cpc_subarg, "cpc%u", i + 1);
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cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
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if (cpc_args == 0)
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continue;
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}
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cpccfg0 = in_be32(&cpc->cpccfg0);
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size += CPC_CFG0_SZ_K(cpccfg0);
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
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setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
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setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
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setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006379
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if (has_erratum_a006379()) {
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setbits_be32(&cpc->cpchdbcr0,
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CPC_HDBCR0_SPLRU_LEVEL_EN);
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}
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#endif
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out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
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/* Read back to sync write */
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in_be32(&cpc->cpccsr0);
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}
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puts("Corenet Platform Cache: ");
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print_size(size * 1024, " enabled\n");
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}
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static void invalidate_cpc(void)
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{
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int i;
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cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
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for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
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/* skip CPC when it used as all SRAM */
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if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
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continue;
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/* Flash invalidate the CPC and clear all the locks */
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out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
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while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
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;
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}
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}
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#else
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#define enable_cpc()
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#define invalidate_cpc()
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#define disable_cpc_sram()
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#endif /* CONFIG_SYS_FSL_CPC */
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map
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* initialize a bunch of registers
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*/
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#ifdef CONFIG_FSL_CORENET
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static void corenet_tb_init(void)
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{
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volatile ccsr_rcpm_t *rcpm =
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(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
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volatile ccsr_pic_t *pic =
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(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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u32 whoami = in_be32(&pic->whoami);
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/* Enable the timebase register for this core */
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out_be32(&rcpm->ctbenrl, (1 << whoami));
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
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void fsl_erratum_a007212_workaround(void)
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{
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_pll_ratio;
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u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
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u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
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u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
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u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
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u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
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#endif
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#endif
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/*
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* Even this workaround applies to selected version of SoCs, it is
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* safe to apply to all versions, with the limitation of odd ratios.
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* If RCW has disabled DDR PLL, we have to apply this workaround,
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* otherwise DDR will not work.
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*/
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ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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/* check if RCW sets ratio to 0, required by this workaround */
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if (ddr_pll_ratio != 0)
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return;
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ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
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FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
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/* check if reserved bits have the desired ratio */
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if (ddr_pll_ratio == 0) {
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printf("Error: Unknown DDR PLL ratio!\n");
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return;
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}
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ddr_pll_ratio >>= 1;
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setbits_be32(plldadcr1, 0x02000001);
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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setbits_be32(plldadcr2, 0x02000001);
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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setbits_be32(plldadcr3, 0x02000001);
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#endif
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#endif
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setbits_be32(dpdovrcr4, 0xe0000000);
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out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
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#endif
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#endif
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udelay(100);
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clrbits_be32(plldadcr1, 0x02000001);
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
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clrbits_be32(plldadcr2, 0x02000001);
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#if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
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clrbits_be32(plldadcr3, 0x02000001);
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#endif
|
|
#endif
|
|
clrbits_be32(dpdovrcr4, 0xe0000000);
|
|
}
|
|
#endif
|
|
|
|
ulong cpu_init_f(void)
|
|
{
|
|
extern void m8560_cpm_reset (void);
|
|
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
|
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
#endif
|
|
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
|
|
struct law_entry law;
|
|
#endif
|
|
#ifdef CONFIG_ARCH_MPC8548
|
|
ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
|
|
uint svr = get_svr();
|
|
|
|
/*
|
|
* CPU2 errata workaround: A core hang possible while executing
|
|
* a msync instruction and a snoopable transaction from an I/O
|
|
* master tagged to make quick forward progress is present.
|
|
* Fixed in silicon rev 2.1.
|
|
*/
|
|
if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
|
|
out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
|
|
#endif
|
|
|
|
disable_tlb(14);
|
|
disable_tlb(15);
|
|
|
|
#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
|
|
/* Disable the LAW created for NOR flash by the PBI commands */
|
|
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
|
|
if (law.index != -1)
|
|
disable_law(law.index);
|
|
|
|
#if defined(CONFIG_SYS_CPC_REINIT_F)
|
|
disable_cpc_sram();
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_CPM2
|
|
config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
|
|
#endif
|
|
|
|
init_early_memctl_regs();
|
|
|
|
#if defined(CONFIG_CPM2)
|
|
m8560_cpm_reset();
|
|
#endif
|
|
|
|
#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
|
|
/* Config QE ioports */
|
|
config_qe_ioports();
|
|
#endif
|
|
|
|
#if defined(CONFIG_FSL_DMA)
|
|
dma_init();
|
|
#endif
|
|
#ifdef CONFIG_FSL_CORENET
|
|
corenet_tb_init();
|
|
#endif
|
|
init_used_tlb_cams();
|
|
|
|
/* Invalidate the CPC before DDR gets enabled */
|
|
invalidate_cpc();
|
|
|
|
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
|
/* set DCSRCR so that DCSR space is 1G */
|
|
setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
|
|
in_be32(&gur->dcsrcr);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
|
|
fsl_erratum_a007212_workaround();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Implement a dummy function for those platforms w/o SERDES */
|
|
static void __fsl_serdes__init(void)
|
|
{
|
|
return ;
|
|
}
|
|
__attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
|
|
|
|
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
|
int enable_cluster_l2(void)
|
|
{
|
|
int i = 0;
|
|
u32 cluster, svr = get_svr();
|
|
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
struct ccsr_cluster_l2 __iomem *l2cache;
|
|
|
|
/* only the L2 of first cluster should be enabled as expected on T4080,
|
|
* but there is no EOC in the first cluster as HW sake, so return here
|
|
* to skip enabling L2 cache of the 2nd cluster.
|
|
*/
|
|
if (SVR_SOC_VER(svr) == SVR_T4080)
|
|
return 0;
|
|
|
|
cluster = in_be32(&gur->tp_cluster[i].lower);
|
|
if (cluster & TP_CLUSTER_EOC)
|
|
return 0;
|
|
|
|
/* The first cache has already been set up, so skip it */
|
|
i++;
|
|
|
|
/* Look through the remaining clusters, and set up their caches */
|
|
do {
|
|
int j, cluster_valid = 0;
|
|
|
|
l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
|
|
|
|
cluster = in_be32(&gur->tp_cluster[i].lower);
|
|
|
|
/* check that at least one core/accel is enabled in cluster */
|
|
for (j = 0; j < 4; j++) {
|
|
u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
|
|
u32 type = in_be32(&gur->tp_ityp[idx]);
|
|
|
|
if ((type & TP_ITYP_AV) &&
|
|
TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
|
|
cluster_valid = 1;
|
|
}
|
|
|
|
if (cluster_valid) {
|
|
/* set stash ID to (cluster) * 2 + 32 + 1 */
|
|
clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
|
|
|
|
printf("enable l2 for cluster %d %p\n", i, l2cache);
|
|
|
|
out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
|
|
while ((in_be32(&l2cache->l2csr0)
|
|
& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
|
|
;
|
|
out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
|
|
}
|
|
i++;
|
|
} while (!(cluster & TP_CLUSTER_EOC));
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Initialize L2 as cache.
|
|
*/
|
|
int l2cache_init(void)
|
|
{
|
|
__maybe_unused u32 svr = get_svr();
|
|
#ifdef CONFIG_L2_CACHE
|
|
ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
|
|
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
|
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
|
|
#endif
|
|
|
|
puts ("L2: ");
|
|
|
|
#if defined(CONFIG_L2_CACHE)
|
|
volatile uint cache_ctl;
|
|
uint ver;
|
|
u32 l2siz_field;
|
|
|
|
ver = SVR_SOC_VER(svr);
|
|
|
|
asm("msync;isync");
|
|
cache_ctl = l2cache->l2ctl;
|
|
|
|
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
|
|
if (cache_ctl & MPC85xx_L2CTL_L2E) {
|
|
/* Clear L2 SRAM memory-mapped base address */
|
|
out_be32(&l2cache->l2srbar0, 0x0);
|
|
out_be32(&l2cache->l2srbar1, 0x0);
|
|
|
|
/* set MBECCDIS=0, SBECCDIS=0 */
|
|
clrbits_be32(&l2cache->l2errdis,
|
|
(MPC85xx_L2ERRDIS_MBECC |
|
|
MPC85xx_L2ERRDIS_SBECC));
|
|
|
|
/* set L2E=0, L2SRAM=0 */
|
|
clrbits_be32(&l2cache->l2ctl,
|
|
(MPC85xx_L2CTL_L2E |
|
|
MPC85xx_L2CTL_L2SRAM_ENTIRE));
|
|
}
|
|
#endif
|
|
|
|
l2siz_field = (cache_ctl >> 28) & 0x3;
|
|
|
|
switch (l2siz_field) {
|
|
case 0x0:
|
|
printf(" unknown size (0x%08x)\n", cache_ctl);
|
|
return -1;
|
|
break;
|
|
case 0x1:
|
|
if (ver == SVR_8540 || ver == SVR_8560 ||
|
|
ver == SVR_8541 || ver == SVR_8555) {
|
|
puts("128 KiB ");
|
|
/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
|
|
cache_ctl = 0xc4000000;
|
|
} else {
|
|
puts("256 KiB ");
|
|
cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
|
|
}
|
|
break;
|
|
case 0x2:
|
|
if (ver == SVR_8540 || ver == SVR_8560 ||
|
|
ver == SVR_8541 || ver == SVR_8555) {
|
|
puts("256 KiB ");
|
|
/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
|
|
cache_ctl = 0xc8000000;
|
|
} else {
|
|
puts("512 KiB ");
|
|
/* set L2E=1, L2I=1, & L2SRAM=0 */
|
|
cache_ctl = 0xc0000000;
|
|
}
|
|
break;
|
|
case 0x3:
|
|
puts("1024 KiB ");
|
|
/* set L2E=1, L2I=1, & L2SRAM=0 */
|
|
cache_ctl = 0xc0000000;
|
|
break;
|
|
}
|
|
|
|
if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
|
|
puts("already enabled");
|
|
#if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
|
|
u32 l2srbar = l2cache->l2srbar0;
|
|
if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
|
|
&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
|
|
l2srbar = CONFIG_SYS_INIT_L2_ADDR;
|
|
l2cache->l2srbar0 = l2srbar;
|
|
printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
|
|
}
|
|
#endif /* CONFIG_SYS_INIT_L2_ADDR */
|
|
puts("\n");
|
|
} else {
|
|
asm("msync;isync");
|
|
l2cache->l2ctl = cache_ctl; /* invalidate & enable */
|
|
asm("msync;isync");
|
|
puts("enabled\n");
|
|
}
|
|
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
|
|
if (SVR_SOC_VER(svr) == SVR_P2040) {
|
|
puts("N/A\n");
|
|
goto skip_l2;
|
|
}
|
|
|
|
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
|
|
|
|
/* invalidate the L2 cache */
|
|
mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
|
|
while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
|
|
;
|
|
|
|
#ifdef CONFIG_SYS_CACHE_STASHING
|
|
/* set stash id to (coreID) * 2 + 32 + L2 (1) */
|
|
mtspr(SPRN_L2CSR1, (32 + 1));
|
|
#endif
|
|
|
|
/* enable the cache */
|
|
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
|
|
|
|
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
|
|
while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
|
|
;
|
|
print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
|
|
}
|
|
|
|
skip_l2:
|
|
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
|
|
if (l2cache->l2csr0 & L2CSR0_L2E)
|
|
print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
|
|
" enabled\n");
|
|
|
|
enable_cluster_l2();
|
|
#else
|
|
puts("disabled\n");
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
*
|
|
* The newer 8548, etc, parts have twice as much cache, but
|
|
* use the same bit-encoding as the older 8555, etc, parts.
|
|
*
|
|
*/
|
|
int cpu_init_r(void)
|
|
{
|
|
__maybe_unused u32 svr = get_svr();
|
|
#ifdef CONFIG_SYS_LBC_LCRR
|
|
fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
|
|
#endif
|
|
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
|
|
extern int spin_table_compat;
|
|
const char *spin;
|
|
#endif
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
|
|
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
|
|
#endif
|
|
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
|
|
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
|
|
/*
|
|
* CPU22 and NMG_CPU_A011 share the same workaround.
|
|
* CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
|
|
* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
|
|
* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
|
|
* fixed in 2.0. NMG_CPU_A011 is activated by default and can
|
|
* be disabled by hwconfig with syntax:
|
|
*
|
|
* fsl_cpu_a011:disable
|
|
*/
|
|
extern int enable_cpu_a011_workaround;
|
|
#ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
|
|
enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
|
|
#else
|
|
char buffer[HWCONFIG_BUFFER_SIZE];
|
|
char *buf = NULL;
|
|
int n, res;
|
|
|
|
n = env_get_f("hwconfig", buffer, sizeof(buffer));
|
|
if (n > 0)
|
|
buf = buffer;
|
|
|
|
res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
|
|
if (res > 0) {
|
|
enable_cpu_a011_workaround = 0;
|
|
} else {
|
|
if (n >= HWCONFIG_BUFFER_SIZE) {
|
|
printf("fsl_cpu_a011 was not found. hwconfig variable "
|
|
"may be too long\n");
|
|
}
|
|
enable_cpu_a011_workaround =
|
|
(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
|
|
(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
|
|
}
|
|
#endif
|
|
if (enable_cpu_a011_workaround) {
|
|
flush_dcache();
|
|
mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
|
|
sync();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A007907
|
|
flush_dcache();
|
|
mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
|
|
sync();
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A005812
|
|
/*
|
|
* A-005812 workaround sets bit 32 of SPR 976 for SoCs running
|
|
* in write shadow mode. Checking DCWS before setting SPR 976.
|
|
*/
|
|
if (mfspr(L1CSR2) & L1CSR2_DCWS)
|
|
mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
|
|
#endif
|
|
|
|
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
|
|
spin = env_get("spin_table_compat");
|
|
if (spin && (*spin == 'n'))
|
|
spin_table_compat = 0;
|
|
else
|
|
spin_table_compat = 1;
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_CORENET
|
|
set_liodns();
|
|
#ifdef CONFIG_SYS_DPAA_QBMAN
|
|
setup_qbman_portals();
|
|
#endif
|
|
#endif
|
|
|
|
l2cache_init();
|
|
#if defined(CONFIG_RAMBOOT_PBL)
|
|
disable_cpc_sram();
|
|
#endif
|
|
enable_cpc();
|
|
#if defined(T1040_TDM_QUIRK_CCSR_BASE)
|
|
enable_tdm_law();
|
|
#endif
|
|
|
|
#ifndef CONFIG_SYS_FSL_NO_SERDES
|
|
/* needs to be in ram since code uses global static vars */
|
|
fsl_serdes_init();
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
|
|
#define MCFGR_AXIPIPE 0x000000f0
|
|
if (IS_SVR_REV(svr, 1, 0))
|
|
sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
|
|
if (IS_SVR_REV(svr, 1, 0)) {
|
|
int i;
|
|
__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
|
|
|
|
for (i = 0; i < 12; i++) {
|
|
p += i + (i > 5 ? 11 : 0);
|
|
out_be32(p, 0x2);
|
|
}
|
|
p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
|
|
out_be32(p, 0x34);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_SRIO
|
|
srio_init();
|
|
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
|
|
char *s = env_get("bootmaster");
|
|
if (s) {
|
|
if (!strcmp(s, "SRIO1")) {
|
|
srio_boot_master(1);
|
|
srio_boot_master_release_slave(1);
|
|
}
|
|
if (!strcmp(s, "SRIO2")) {
|
|
srio_boot_master(2);
|
|
srio_boot_master_release_slave(2);
|
|
}
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_MP)
|
|
setup_mp();
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
|
|
{
|
|
if (SVR_MAJ(svr) < 3) {
|
|
void *p;
|
|
p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
|
|
setbits_be32(p, 1 << (31 - 14));
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_LBC_LCRR
|
|
/*
|
|
* Modify the CLKDIV field of LCRR register to improve the writing
|
|
* speed for NOR flash.
|
|
*/
|
|
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
|
|
__raw_readl(&lbc->lcrr);
|
|
isync();
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
|
|
udelay(100);
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
{
|
|
struct ccsr_usb_phy __iomem *usb_phy1 =
|
|
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
|
if (has_erratum_a006261())
|
|
fsl_erratum_a006261_workaround(usb_phy1);
|
|
#endif
|
|
out_be32(&usb_phy1->usb_enable_override,
|
|
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
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{
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struct ccsr_usb_phy __iomem *usb_phy2 =
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(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
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if (has_erratum_a006261())
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fsl_erratum_a006261_workaround(usb_phy2);
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#endif
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out_be32(&usb_phy2->usb_enable_override,
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CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
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}
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#endif
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|
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#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
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/* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
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* multi-bit ECC errors which has impact on performance, so software
|
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* should disable all ECC reporting from USB1 and USB2.
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*/
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if (IS_SVR_REV(get_svr(), 1, 0)) {
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struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
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(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
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setbits_be32(&dcfg->ecccr1,
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(DCSR_DCFG_ECC_DISABLE_USB1 |
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DCSR_DCFG_ECC_DISABLE_USB2));
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}
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#endif
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|
|
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#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
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struct ccsr_usb_phy __iomem *usb_phy =
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(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
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setbits_be32(&usb_phy->pllprg[1],
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CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
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CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
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|
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
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CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
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|
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
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usb_single_source_clk_configure(usb_phy);
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|
#endif
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|
setbits_be32(&usb_phy->port1.ctrl,
|
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CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
|
|
setbits_be32(&usb_phy->port1.drvvbuscfg,
|
|
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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|
setbits_be32(&usb_phy->port1.pwrfltcfg,
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|
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
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|
setbits_be32(&usb_phy->port2.ctrl,
|
|
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
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|
setbits_be32(&usb_phy->port2.drvvbuscfg,
|
|
CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
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|
setbits_be32(&usb_phy->port2.pwrfltcfg,
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|
CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
|
|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
|
|
if (has_erratum_a006261())
|
|
fsl_erratum_a006261_workaround(usb_phy);
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|
#endif
|
|
|
|
#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
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|
|
|
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
|
|
erratum_a009942_check_cpo();
|
|
#endif
|
|
|
|
#ifdef CONFIG_FMAN_ENET
|
|
fman_enet_init();
|
|
#endif
|
|
|
|
#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
|
|
if (pamu_init() < 0)
|
|
fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
|
|
#endif
|
|
|
|
#ifdef CONFIG_FSL_CAAM
|
|
sec_init();
|
|
|
|
#if defined(CONFIG_ARCH_C29X)
|
|
if ((SVR_SOC_VER(svr) == SVR_C292) ||
|
|
(SVR_SOC_VER(svr) == SVR_C293))
|
|
sec_init_idx(1);
|
|
|
|
if (SVR_SOC_VER(svr) == SVR_C293)
|
|
sec_init_idx(2);
|
|
#endif
|
|
#endif
|
|
|
|
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
|
|
/*
|
|
* For P1022/1013 Rev1.0 silicon, after power on SATA host
|
|
* controller is configured in legacy mode instead of the
|
|
* expected enterprise mode. Software needs to clear bit[28]
|
|
* of HControl register to change to enterprise mode from
|
|
* legacy mode. We assume that the controller is offline.
|
|
*/
|
|
if (IS_SVR_REV(svr, 1, 0) &&
|
|
((SVR_SOC_VER(svr) == SVR_P1022) ||
|
|
(SVR_SOC_VER(svr) == SVR_P1013))) {
|
|
fsl_sata_reg_t *reg;
|
|
|
|
/* first SATA controller */
|
|
reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
|
|
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
|
|
|
|
/* second SATA controller */
|
|
reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
|
|
clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
|
|
}
|
|
#endif
|
|
|
|
init_used_tlb_cams();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void arch_preboot_os(void)
|
|
{
|
|
u32 msr;
|
|
|
|
/*
|
|
* We are changing interrupt offsets and are about to boot the OS so
|
|
* we need to make sure we disable all async interrupts. EE is already
|
|
* disabled by the time we get called.
|
|
*/
|
|
msr = mfmsr();
|
|
msr &= ~(MSR_ME|MSR_CE);
|
|
mtmsr(msr);
|
|
}
|
|
|
|
#if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA)
|
|
int sata_initialize(void)
|
|
{
|
|
if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
|
|
return __sata_initialize();
|
|
|
|
return 1;
|
|
}
|
|
#endif
|
|
|
|
void cpu_secondary_init_r(void)
|
|
{
|
|
#ifdef CONFIG_U_QE
|
|
uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
|
|
#elif defined CONFIG_QE
|
|
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
|
|
#endif
|
|
|
|
#ifdef CONFIG_QE
|
|
qe_init(qe_base);
|
|
qe_reset();
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_BOARD_LATE_INIT
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_CHAIN_OF_TRUST
|
|
fsl_setenv_chain_of_trust();
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|