mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
144 lines
2.9 KiB
C
144 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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/*
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* CPU test
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* Shift instructions: rlwnm
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*
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* The test contains a pre-built table of instructions, operands and
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* expected results. For each table entry, the test will cyclically use
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* different sets of operand registers and result registers.
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*/
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#include <post.h>
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#include "cpu_asm.h"
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#if CONFIG_POST & CONFIG_SYS_POST_CPU
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extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
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ulong op2);
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extern ulong cpu_post_makecr (long v);
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static struct cpu_post_rlwnm_s
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{
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ulong cmd;
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ulong op1;
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ulong op2;
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uchar mb;
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uchar me;
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ulong res;
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} cpu_post_rlwnm_table[] =
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{
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{
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OP_RLWNM,
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0xffff0000,
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24,
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16,
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23,
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0x0000ff00
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},
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};
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static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table);
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int cpu_post_test_rlwnm (void)
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{
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int ret = 0;
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unsigned int i, reg;
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int flag = disable_interrupts();
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for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
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{
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struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
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for (reg = 0; reg < 32 && ret == 0; reg++)
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{
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unsigned int reg0 = (reg + 0) % 32;
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unsigned int reg1 = (reg + 1) % 32;
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unsigned int reg2 = (reg + 2) % 32;
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unsigned int stk = reg < 16 ? 31 : 15;
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unsigned long code[] =
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{
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ASM_STW(stk, 1, -4),
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ASM_ADDI(stk, 1, -24),
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ASM_STW(3, stk, 12),
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ASM_STW(4, stk, 16),
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ASM_STW(reg0, stk, 8),
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ASM_STW(reg1, stk, 4),
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ASM_STW(reg2, stk, 0),
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ASM_LWZ(reg1, stk, 12),
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ASM_LWZ(reg0, stk, 16),
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ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
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ASM_STW(reg2, stk, 12),
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ASM_LWZ(reg2, stk, 0),
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ASM_LWZ(reg1, stk, 4),
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ASM_LWZ(reg0, stk, 8),
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ASM_LWZ(3, stk, 12),
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ASM_ADDI(1, stk, 24),
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ASM_LWZ(stk, 1, -4),
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ASM_BLR,
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};
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unsigned long codecr[] =
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{
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ASM_STW(stk, 1, -4),
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ASM_ADDI(stk, 1, -24),
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ASM_STW(3, stk, 12),
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ASM_STW(4, stk, 16),
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ASM_STW(reg0, stk, 8),
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ASM_STW(reg1, stk, 4),
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ASM_STW(reg2, stk, 0),
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ASM_LWZ(reg1, stk, 12),
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ASM_LWZ(reg0, stk, 16),
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ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
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BIT_C,
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ASM_STW(reg2, stk, 12),
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ASM_LWZ(reg2, stk, 0),
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ASM_LWZ(reg1, stk, 4),
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ASM_LWZ(reg0, stk, 8),
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ASM_LWZ(3, stk, 12),
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ASM_ADDI(1, stk, 24),
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ASM_LWZ(stk, 1, -4),
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ASM_BLR,
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};
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ulong res;
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ulong cr;
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if (ret == 0)
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{
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cr = 0;
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cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
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ret = res == test->res && cr == 0 ? 0 : -1;
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if (ret != 0)
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{
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post_log ("Error at rlwnm test %d !\n", i);
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}
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}
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if (ret == 0)
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{
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cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
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ret = res == test->res &&
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(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
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if (ret != 0)
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{
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post_log ("Error at rlwnm test %d !\n", i);
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}
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}
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}
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}
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if (flag)
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enable_interrupts();
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return ret;
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}
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#endif
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