mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
fd6e425be2
Add sfc and flash node to device tree and config options to enable support for booting from SPI NOR flash on Radxa ROCK 5 Model B. Similar to RK3568 the BootRom in RK3588 can read all data and look for idbloader at 0x8000, same as on SD and eMMC. Use the rksd format and modify the mkimage offset to generate a bootable u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The FIT image is loaded from 0x60000. => sf probe SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB => load mmc 1:1 10000000 u-boot-rockchip-spi.bin 1492992 bytes read in 129 ms (11 MiB/s) => sf update $fileaddr 0 $filesize device 0 offset 0x0, size 0x16c800 1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does not match the expected value of 3 (SPINOR) used by other SoCs. Instead a value of 6 is read back, add a new enum value to handle this new bootsource id. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Eugen Hristev <eugen.hristev@collabora.com> Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
211 lines
3.2 KiB
Text
211 lines
3.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Collabora Ltd.
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*/
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#include "rk3588-u-boot.dtsi"
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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aliases {
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mmc1 = &sdmmc;
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spi0 = &sfc;
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};
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
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};
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vcc5v0_host: vcc5v0-host-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc5v0_host";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&vcc5v0_host_en>;
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vin-supply = <&vcc5v0_sys>;
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};
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};
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&combphy0_ps {
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status = "okay";
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};
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&emmc_bus8 {
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bootph-all;
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};
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&emmc_clk {
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bootph-all;
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};
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&emmc_cmd {
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bootph-all;
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};
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&emmc_data_strobe {
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bootph-all;
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};
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&emmc_rstnout {
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bootph-all;
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};
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&fspim2_pins {
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bootph-all;
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};
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&pcie2x1l2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
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reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&pinctrl {
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bootph-all;
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pcie {
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pcie_reset_h: pcie-reset-h {
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rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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pcie2x1l2_pins: pcie2x1l2-pins {
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rockchip,pins = <3 RK_PC7 4 &pcfg_pull_none>,
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<3 RK_PD0 4 &pcfg_pull_none>;
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};
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};
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usb {
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vcc5v0_host_en: vcc5v0-host-en {
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rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&pcfg_pull_none {
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bootph-all;
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};
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&pcfg_pull_up_drv_level_2 {
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bootph-all;
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};
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&pcfg_pull_up {
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bootph-all;
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};
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&sdmmc {
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bus-width = <4>;
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status = "okay";
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};
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&sdmmc_bus4 {
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bootph-all;
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};
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&sdmmc_clk {
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bootph-all;
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};
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&sdmmc_cmd {
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bootph-all;
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};
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&sdmmc_det {
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bootph-all;
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};
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&sdhci {
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
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};
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&sfc {
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bootph-pre-ram;
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u-boot,spl-sfc-no-dma;
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pinctrl-names = "default";
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pinctrl-0 = <&fspim2_pins>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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flash@0 {
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bootph-pre-ram;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <24000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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};
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};
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&uart2m0_xfer {
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bootph-all;
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};
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&usb_host0_ehci {
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companion = <&usb_host0_ohci>;
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phys = <&u2phy2_host>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usb_host0_ohci {
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phys = <&u2phy2_host>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usb2phy2_grf {
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status = "okay";
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};
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&u2phy2 {
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resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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reset-names = "phy", "apb";
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clock-output-names = "usb480m_phy2";
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status = "okay";
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};
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&u2phy2_host {
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phy-supply = <&vcc5v0_host>;
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status = "okay";
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};
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&usb_host1_ehci {
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companion = <&usb_host1_ohci>;
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phys = <&u2phy3_host>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usb_host1_ohci {
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phys = <&u2phy3_host>;
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phy-names = "usb2-phy";
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status = "okay";
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};
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&usb2phy3_grf {
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status = "okay";
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};
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&u2phy3 {
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resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
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reset-names = "phy", "apb";
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clock-output-names = "usb480m_phy3";
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status = "okay";
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};
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&u2phy3_host {
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phy-supply = <&vcc5v0_host>;
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status = "okay";
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};
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