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https://github.com/AsahiLinux/u-boot
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07011890a6
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Angelo Dureghello <angelo@kernel-space.org>
176 lines
4.9 KiB
C
176 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#include <cpu_func.h>
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#include <init.h>
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#include <watchdog.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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#if defined(CONFIG_CMD_NET)
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#include <config.h>
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#include <net.h>
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#include <asm/fec.h>
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#endif
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/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
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#ifdef CONFIG_M5235
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#define out_be_fbcs_reg out_be16
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#else
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#define out_be_fbcs_reg out_be32
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#endif
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/*
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* Breath some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f(void)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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wdog_t *wdog = (wdog_t *) MMAP_WDOG;
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scm_t *scm = (scm_t *) MMAP_SCM;
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/* watchdog is enabled by default - disable the watchdog */
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#ifndef CONFIG_WATCHDOG
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out_be16(&wdog->cr, 0);
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#endif
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out_be32(&scm->rambar, CFG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
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/* Port configuration */
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out_8(&gpio->par_cs, 0);
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#if (defined(CFG_SYS_CS0_BASE) && defined(CFG_SYS_CS0_MASK) && defined(CFG_SYS_CS0_CTRL))
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out_be_fbcs_reg(&fbcs->csar0, CFG_SYS_CS0_BASE);
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out_be_fbcs_reg(&fbcs->cscr0, CFG_SYS_CS0_CTRL);
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out_be32(&fbcs->csmr0, CFG_SYS_CS0_MASK);
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#endif
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#if (defined(CFG_SYS_CS1_BASE) && defined(CFG_SYS_CS1_MASK) && defined(CFG_SYS_CS1_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
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out_be_fbcs_reg(&fbcs->csar1, CFG_SYS_CS1_BASE);
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out_be_fbcs_reg(&fbcs->cscr1, CFG_SYS_CS1_CTRL);
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out_be32(&fbcs->csmr1, CFG_SYS_CS1_MASK);
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#endif
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#if (defined(CFG_SYS_CS2_BASE) && defined(CFG_SYS_CS2_MASK) && defined(CFG_SYS_CS2_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
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out_be_fbcs_reg(&fbcs->csar2, CFG_SYS_CS2_BASE);
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out_be_fbcs_reg(&fbcs->cscr2, CFG_SYS_CS2_CTRL);
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out_be32(&fbcs->csmr2, CFG_SYS_CS2_MASK);
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#endif
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#if (defined(CFG_SYS_CS3_BASE) && defined(CFG_SYS_CS3_MASK) && defined(CFG_SYS_CS3_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
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out_be_fbcs_reg(&fbcs->csar3, CFG_SYS_CS3_BASE);
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out_be_fbcs_reg(&fbcs->cscr3, CFG_SYS_CS3_CTRL);
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out_be32(&fbcs->csmr3, CFG_SYS_CS3_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
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out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
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out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
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out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
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out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
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out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
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out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
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out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
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out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
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out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
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#endif
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#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
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setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
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out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
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out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
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out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
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#endif
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#ifdef CONFIG_SYS_I2C_FSL
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CFG_SYS_I2C_PINMUX_REG &= CFG_SYS_I2C_PINMUX_CLR;
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CFG_SYS_I2C_PINMUX_REG |= CFG_SYS_I2C_PINMUX_SET;
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#endif
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icache_enable();
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}
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/*
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* initialize higher level parts of CPU like timers
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*/
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int cpu_init_r(void)
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{
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return (0);
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}
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void uart_port_conf(int port)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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/* Setup Ports: */
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switch (port) {
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case 0:
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clrbits_be16(&gpio->par_uart,
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GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
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setbits_be16(&gpio->par_uart,
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GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
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break;
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case 1:
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clrbits_be16(&gpio->par_uart,
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GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
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setbits_be16(&gpio->par_uart,
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GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
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break;
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case 2:
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#ifdef CONFIG_SYS_UART2_PRI_GPIO
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clrbits_be16(&gpio->par_uart,
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GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
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setbits_be16(&gpio->par_uart,
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GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
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#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
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clrbits_8(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
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setbits_8(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
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#endif
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break;
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}
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}
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#if defined(CONFIG_CMD_NET)
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int fecpin_setclear(fec_info_t *info, int setclear)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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if (setclear) {
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setbits_8(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_EMDC_FECEMDC |
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GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
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} else {
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clrbits_8(&gpio->par_feci2c,
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GPIO_PAR_FECI2C_EMDC_MASK |
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GPIO_PAR_FECI2C_EMDIO_MASK);
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}
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return 0;
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}
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#endif
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