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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
174 lines
4.4 KiB
C
174 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/bcm63xx/cpu.c:
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <ram.h>
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#include <asm/io.h>
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#define SDRAM_CFG_REG 0x0
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#define SDRAM_CFG_COL_SHIFT 4
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#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
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#define SDRAM_CFG_ROW_SHIFT 6
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#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
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#define SDRAM_CFG_32B_SHIFT 10
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#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
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#define SDRAM_CFG_BANK_SHIFT 13
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#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
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#define SDRAM_6318_SPACE_SHIFT 4
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#define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
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#define MEMC_CFG_REG 0x4
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#define MEMC_CFG_32B_SHIFT 1
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#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
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#define MEMC_CFG_COL_SHIFT 3
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#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
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#define MEMC_CFG_ROW_SHIFT 6
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#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
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#define DDR_CSEND_REG 0x8
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struct bmips_ram_priv;
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struct bmips_ram_hw {
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ulong (*get_ram_size)(struct bmips_ram_priv *);
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};
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struct bmips_ram_priv {
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void __iomem *regs;
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const struct bmips_ram_hw *hw;
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};
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static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
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{
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u32 val;
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val = readl_be(priv->regs + SDRAM_CFG_REG);
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val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
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return (1 << (val + 20));
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}
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static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
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{
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return readl_be(priv->regs + DDR_CSEND_REG) << 24;
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}
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static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
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unsigned int is_32b, unsigned int banks)
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{
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rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
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cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
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is_32b += 1;
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return 1 << (cols + rows + is_32b + banks);
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}
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static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
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{
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unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
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u32 val;
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val = readl_be(priv->regs + SDRAM_CFG_REG);
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rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
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cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
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is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
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banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
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return bmips_dram_size(cols, rows, is_32b, banks);
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}
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static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
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{
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unsigned int cols = 0, rows = 0, is_32b = 0;
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u32 val;
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val = readl_be(priv->regs + MEMC_CFG_REG);
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rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
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cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
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is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
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return bmips_dram_size(cols, rows, is_32b, 2);
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}
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static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
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{
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struct bmips_ram_priv *priv = dev_get_priv(dev);
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const struct bmips_ram_hw *hw = priv->hw;
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info->base = 0x80000000;
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info->size = hw->get_ram_size(priv);
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return 0;
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}
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static const struct ram_ops bmips_ram_ops = {
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.get_info = bmips_ram_get_info,
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};
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static const struct bmips_ram_hw bmips_ram_bcm6318 = {
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.get_ram_size = bcm6318_get_ram_size,
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};
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static const struct bmips_ram_hw bmips_ram_bcm6328 = {
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.get_ram_size = bcm6328_get_ram_size,
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};
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static const struct bmips_ram_hw bmips_ram_bcm6338 = {
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.get_ram_size = bcm6338_get_ram_size,
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};
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static const struct bmips_ram_hw bmips_ram_bcm6358 = {
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.get_ram_size = bcm6358_get_ram_size,
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};
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static const struct udevice_id bmips_ram_ids[] = {
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{
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.compatible = "brcm,bcm6318-mc",
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.data = (ulong)&bmips_ram_bcm6318,
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}, {
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.compatible = "brcm,bcm6328-mc",
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.data = (ulong)&bmips_ram_bcm6328,
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}, {
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.compatible = "brcm,bcm6338-mc",
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.data = (ulong)&bmips_ram_bcm6338,
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}, {
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.compatible = "brcm,bcm6358-mc",
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.data = (ulong)&bmips_ram_bcm6358,
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}, { /* sentinel */ }
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};
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static int bmips_ram_probe(struct udevice *dev)
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{
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struct bmips_ram_priv *priv = dev_get_priv(dev);
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const struct bmips_ram_hw *hw =
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(const struct bmips_ram_hw *)dev_get_driver_data(dev);
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fdt_addr_t addr;
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fdt_size_t size;
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addr = devfdt_get_addr_size_index(dev, 0, &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->regs = ioremap(addr, size);
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priv->hw = hw;
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return 0;
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}
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U_BOOT_DRIVER(bmips_ram) = {
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.name = "bmips-mc",
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.id = UCLASS_RAM,
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.of_match = bmips_ram_ids,
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.probe = bmips_ram_probe,
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.priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
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.ops = &bmips_ram_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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