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Versal NET mini configuration is designed for running memory test. Current output is on DCC but changing serial0 alias to pl011 will move console to serial port. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aec3f41a4cc48c45b8f07dd6e423d5838dbcc9d7.1663589964.git.michal.simek@amd.com
67 lines
1.2 KiB
Text
67 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for Xilinx Versal NET
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*
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* Copyright (C) 2021 - 2022, Xilinx, Inc.
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* Copyright (C) 2022, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "xlnx,versal-net-mini";
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model = "Xilinx Versal NET MINI";
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#address-cells = <2>;
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#size-cells = <2>;
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memory: memory@0 {
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reg = <0 0xBBF00000 0 0x100000>, <0 0 0 0x80000000>;
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device_type = "memory";
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};
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aliases {
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/* serial0 = &serial0; */
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serial0 = &dcc;
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};
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chosen {
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stdout-path = "serial0:115200";
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};
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clk1: clk1 {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <1000000>;
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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amba: axi {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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serial0: serial@f1920000 {
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u-boot,dm-pre-reloc;
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0xf1920000 0 0x1000>;
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reg-io-width = <4>;
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clock-names = "uartclk", "apb_pclk";
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clocks = <&clk1>, <&clk1>;
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clock = <1000000>;
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current-speed = <115200>;
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skip-init;
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};
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};
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};
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