mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 10:48:51 +00:00
69d9eda4da
It is quite confusing that CONFIG_SYS_I2C selects the legacy I2C and CONFIG_DM_I2C selects the current I2C. The deadline to migrate I2C is less than a year away. Also we want to have a CONFIG_I2C for U-Boot proper just like we have CONFIG_SPL_I2C for SPL, so we can simplify the Makefile rules. Rename this symbol so it is clear it is going away. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
240 lines
7.4 KiB
C
240 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*/
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/*
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* Corenet DS style board configuration file
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*/
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#ifndef __T4QDS_H
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#define __T4QDS_H
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/* High Level Configuration Options */
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#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
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#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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#define CONFIG_PCIE1 /* PCIE controller 1 */
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#define CONFIG_PCIE2 /* PCIE controller 2 */
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#define CONFIG_PCIE3 /* PCIE controller 3 */
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
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#define CONFIG_SYS_SRIO
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#define CONFIG_SRIO1 /* SRIO port 1 */
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#define CONFIG_SRIO2 /* SRIO port 2 */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_SYS_CACHE_STASHING
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#define CONFIG_BTB /* toggle branch predition */
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#ifdef CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_ENABLE_36BIT_PHYS
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
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#define CONFIG_SYS_L3_SIZE (512 << 10)
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#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
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#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
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#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
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#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
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#define CONFIG_SYS_DCSRBAR 0xf0000000
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
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/*
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* DDR Setup
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*/
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_DDR_SPD
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/*
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* IFC Definitions
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*/
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#define CONFIG_SYS_FLASH_BASE 0xe0000000
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#endif
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#define CONFIG_HWCONFIG
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM
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#define CONFIG_SYS_INIT_RAM_LOCK
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
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/* The assembler doesn't like typecast */
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
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/* I2C */
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#define CONFIG_SYS_I2C_LEGACY
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
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/*
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* RapidIO
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
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#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
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#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
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/* controller 2, Slot 2, tgtid 2, Base address 201000 */
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#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
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#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
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/* controller 3, Slot 1, tgtid 1, Base address 202000 */
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#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
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#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
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#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
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#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
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#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
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/* controller 4, Base address 203000 */
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#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
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#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
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#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
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#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#endif /* CONFIG_PCI */
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/* SATA */
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#ifdef CONFIG_FSL_SATA_V2
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA1
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#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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#define CONFIG_LBA48
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#endif
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#ifdef CONFIG_FMAN_ENET
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#define CONFIG_ETHPRIME "FM1@DTSEC1"
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#endif
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/*
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* Environment
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*/
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#define CONFIG_LOADS_ECHO /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 64 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#ifdef CONFIG_CMD_KGDB
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_ROOTPATH "/opt/nfsroot"
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
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/* default location for tftp and bootm */
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#define CONFIG_LOADADDR 1000000
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#define CONFIG_HVBOOT \
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"setenv bootargs config-addr=0x60000000; " \
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"bootm 0x01000000 - 0x00f00000"
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#endif /* __CONFIG_H */
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