Pratyush Yadav b862765c7c mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode ... The xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in Octal DTR mode. Use that information to send the correct Read SR command. Some controllers might have trouble reading just 1 byte in DTR mode. So, when we are in DTR mode read 2 bytes and discard the second. This shows no side effects with the two flashes I tested: Micron mt35xu512aba and Cypress s28hs512t. Update Read FSR to mimic Read SR because they share the same characteristics. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>		2021-06-28 12:02:39 +05:30
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fsl_espi_spl.c	common: Move hang() to the same header as panic()	2020-01-17 17:53:40 -05:00
Kconfig	mtd: spi-nor-core: Rework hwcaps selection	2021-06-28 11:59:35 +05:30
Makefile	spi: Allow separate control of SPI_FLASH_TINY for SPL/TPL	2020-08-03 22:19:54 -04:00
sandbox.c	dm: Avoid accessing seq directly	2020-12-18 20:32:21 -07:00
sf-uclass.c	sf: Support querying write-protect	2021-03-27 15:04:31 +13:00
sf_dataflash.c	dm: treewide: Rename auto_alloc_size members to be shorter	2020-12-13 08:00:25 -07:00
sf_internal.h	mtd: spi-nor-core: Add support for DTR protocol	2021-06-28 12:00:32 +05:30
sf_mtd.c	mtd: spi-nor: fill-in mtd->dev member	2021-06-24 11:53:50 +05:30
sf_probe.c	mtd: spi-nor: allow registering multiple MTDs when DM is enabled	2021-06-24 11:53:31 +05:30
spi-nor-core.c	mtd: spi-nor-core: Prepare Read SR and FSR for Octal DTR mode	2021-06-28 12:02:39 +05:30
spi-nor-ids.c	mtd: spi-nor-ids: Add Macronix MX66UW2G345G	2021-06-22 13:53:24 +05:30
spi-nor-tiny.c	mtd: spi-nor-core: Add a ->setup() hook	2021-06-28 11:58:10 +05:30