mirror of
https://github.com/AsahiLinux/u-boot
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ef38b42364
%s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp> Reviewed-by: Stefan Roese <sr@denx.de>
148 lines
5 KiB
C
148 lines
5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR_ML_WRAPPER_H
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#define _DDR_ML_WRAPPER_H
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#include <common.h>
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
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#define INTER_REGS_BASE SOC_REGS_PHY_BASE
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#endif
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/*
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* MV_DEBUG_INIT need to be defines, otherwise the output of the
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* DDR2 training code is not complete and misleading
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*/
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#define MV_DEBUG_INIT
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#ifdef MV_DEBUG_INIT
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#define DEBUG_INIT_S(s) puts(s)
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#define DEBUG_INIT_D(d, l) printf("%x", d)
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#define DEBUG_INIT_D_10(d, l) printf("%d", d)
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#else
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#define DEBUG_INIT_S(s)
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#define DEBUG_INIT_D(d, l)
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#define DEBUG_INIT_D_10(d, l)
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#endif
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#ifdef MV_DEBUG_INIT_FULL
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#define DEBUG_INIT_FULL_S(s) puts(s)
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#define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
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#define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
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#define DEBUG_WR_REG(reg, val) \
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{ DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
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DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
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#define DEBUG_RD_REG(reg, val) \
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{ DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
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DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
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#else
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#define DEBUG_INIT_FULL_S(s)
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#define DEBUG_INIT_FULL_D(d, l)
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#define DEBUG_INIT_FULL_D_10(d, l)
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#define DEBUG_WR_REG(reg, val)
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#define DEBUG_RD_REG(reg, val)
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#endif
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#define DEBUG_INIT_FULL_C(s, d, l) \
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{ DEBUG_INIT_FULL_S(s); \
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DEBUG_INIT_FULL_D(d, l); \
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DEBUG_INIT_FULL_S("\n"); }
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#define DEBUG_INIT_C(s, d, l) \
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{ DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
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/*
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* Debug (Enable/Disable modules) and Error report
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*/
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#ifdef BASIC_DEBUG
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#define MV_DEBUG_WL
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#define MV_DEBUG_RL
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#define MV_DEBUG_DQS_RESULTS
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#endif
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#ifdef FULL_DEBUG
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#define MV_DEBUG_WL
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#define MV_DEBUG_RL
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#define MV_DEBUG_DQS
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#define MV_DEBUG_PBS
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#define MV_DEBUG_DFS
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#define MV_DEBUG_MAIN_FULL
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#define MV_DEBUG_DFS_FULL
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#define MV_DEBUG_DQS_FULL
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#define MV_DEBUG_RL_FULL
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#define MV_DEBUG_WL_FULL
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#endif
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/* The following is a list of Marvell status */
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#define MV_ERROR (-1)
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#define MV_OK (0x00) /* Operation succeeded */
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#define MV_FAIL (0x01) /* Operation failed */
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#define MV_BAD_VALUE (0x02) /* Illegal value (general) */
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#define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
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#define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
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#define MV_BAD_PTR (0x05) /* Illegal pointer value */
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#define MV_BAD_SIZE (0x06) /* Illegal size */
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#define MV_BAD_STATE (0x07) /* Illegal state of state machine */
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#define MV_SET_ERROR (0x08) /* Set operation failed */
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#define MV_GET_ERROR (0x09) /* Get operation failed */
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#define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
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#define MV_NOT_FOUND (0x0b) /* Item not found */
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#define MV_NO_MORE (0x0c) /* No more items found */
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#define MV_NO_SUCH (0x0d) /* No such item */
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#define MV_TIMEOUT (0x0e) /* Time Out */
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#define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
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#define MV_NOT_SUPPORTED (0x10) /* This request is not support */
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#define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
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#define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
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#define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
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#define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
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#define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
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#define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
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#define MV_HW_ERROR (0x17) /* Hardware error */
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#define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
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#define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
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#define MV_NOT_READY (0x1a) /* The other side is not ready yet */
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#define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
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#define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
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#define MV_NOT_STARTED (0x1d) /* Not started yet */
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#define MV_BUSY (0x1e) /* Item is busy. */
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#define MV_TERMINATE (0x1f) /* Item terminates it's work. */
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#define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
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#define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
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#define MV_WRITE_PROTECT (0x22) /* Write protected */
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#define MV_INVALID (int)(-1)
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/*
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* Accessor functions for the registers
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*/
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static inline void reg_write(u32 addr, u32 val)
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{
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writel(val, INTER_REGS_BASE + addr);
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}
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static inline u32 reg_read(u32 addr)
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{
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return readl(INTER_REGS_BASE + addr);
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}
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static inline void reg_bit_set(u32 addr, u32 mask)
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{
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setbits_le32(INTER_REGS_BASE + addr, mask);
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}
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static inline void reg_bit_clr(u32 addr, u32 mask)
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{
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clrbits_le32(INTER_REGS_BASE + addr, mask);
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}
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#endif /* _DDR_ML_WRAPPER_H */
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