mirror of
https://github.com/AsahiLinux/u-boot
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4d9253fb76
For the RK3188, the BROM will attempt to load up the first stage image (SPL for the RK3188) in two steps: first 1KB to offset 0x800 in the SRAM and then the remainder to offset 0xc00 in the SRAM. It always enters at 0x804, though. With this changeset, the RK3188 boot removes the TPL (stub) stage and builds a single SPL binary that utilizes the early back-to-bootrom via the boot0-hook. Consequently, the passing of the saved boot params via pmu->os_reg[2] is also removed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
200 lines
6.5 KiB
Text
200 lines
6.5 KiB
Text
if ARCH_ROCKCHIP
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config ROCKCHIP_RK3036
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bool "Support Rockchip RK3036"
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select CPU_V7
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select SUPPORT_SPL
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select SPL
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help
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The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
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including NEON and GPU, Mali-400 graphics, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK3188
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bool "Support Rockchip RK3188"
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select CPU_V7
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select SPL_BOARD_INIT if SPL
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select SUPPORT_SPL
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select SUPPORT_TPL
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select SPL
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select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
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select BOARD_LATE_INIT
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select ROCKCHIP_BROM_HELPER
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help
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The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
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including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
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video interfaces, several memory options and video codec support.
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Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
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UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK322X
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bool "Support Rockchip RK3228/RK3229"
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select CPU_V7
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select SUPPORT_SPL
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select SPL
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select ROCKCHIP_BROM_HELPER
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select DEBUG_UART_BOARD_INIT
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help
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The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
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including NEON and GPU, Mali-400 graphics, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
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config ROCKCHIP_RK3288
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bool "Support Rockchip RK3288"
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select CPU_V7
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select SPL_BOARD_INIT if SPL
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select SUPPORT_SPL
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select SPL
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help
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The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3328
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bool "Support Rockchip RK3328"
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select ARM64
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help
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The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RK3368
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bool "Support Rockchip RK3368"
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select ARM64
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select SUPPORT_SPL
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select SUPPORT_TPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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imply SPL_SEPARATE_BSS
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imply SPL_SERIAL_SUPPORT
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imply TPL_SERIAL_SUPPORT
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select DEBUG_UART_BOARD_INIT
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select SYS_NS16550
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help
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The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
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into a big and little cluster with 4 cores each) Cortex-A53 including
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AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
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(for the little cluster), PowerVR G6110 based graphics, one video
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output processor supporting LVDS/HDMI/eDP, several DDR3 options and
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video codec support.
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On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
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I2S, UARTs, SPI, I2C and PWMs.
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if ROCKCHIP_RK3368
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config TPL_LDSCRIPT
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default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds"
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config TPL_TEXT_BASE
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default 0xff8c1000
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config TPL_MAX_SIZE
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default 28672
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config TPL_STACK
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default 0xff8cffff
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endif
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config ROCKCHIP_RK3399
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bool "Support Rockchip RK3399"
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select ARM64
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select SUPPORT_SPL
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select SPL
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select SPL_SEPARATE_BSS
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select SPL_SERIAL_SUPPORT
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select SPL_DRIVERS_MISC_SUPPORT
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select DEBUG_UART_BOARD_INIT
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help
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The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
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and quad-core Cortex-A53.
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including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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video interfaces supporting HDMI and eDP, several DDR3 options
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and video codec support. Peripherals include Gigabit Ethernet,
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USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
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config ROCKCHIP_RV1108
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bool "Support Rockchip RV1108"
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select CPU_V7
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help
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The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
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and a DSP.
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config SPL_ROCKCHIP_BACK_TO_BROM
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bool "SPL returns to bootrom"
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default y if ROCKCHIP_RK3036
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select ROCKCHIP_BROM_HELPER
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depends on SPL
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help
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Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
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SPL will return to the boot rom, which will then load the U-Boot
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binary to keep going on.
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config TPL_ROCKCHIP_BACK_TO_BROM
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bool "TPL returns to bootrom"
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default y if ROCKCHIP_RK3368
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select ROCKCHIP_BROM_HELPER
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depends on TPL
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help
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Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
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SPL will return to the boot rom, which will then load the U-Boot
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binary to keep going on.
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config ROCKCHIP_SPL_RESERVE_IRAM
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hex "Size of IRAM reserved in SPL"
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default 0x4000
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help
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SPL may need reserve memory for firmware loaded by SPL, whose load
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address is in IRAM and may overlay with SPL text area if not
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reserved.
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config ROCKCHIP_BROM_HELPER
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bool
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config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
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bool "SPL requires early-return (for RK3188-style BROM) to BROM"
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depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
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help
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Some Rockchip BROM variants (e.g. on the RK3188) load the
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first stage in segments and enter multiple times. E.g. on
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the RK3188, the first 1KB of the first stage are loaded
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first and entered; after returning to the BROM, the
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remainder of the first stage is loaded, but the BROM
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re-enters at the same address/to the same code as previously.
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This enables support code in the BOOT0 hook for the SPL stage
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to allow multiple entries.
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config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
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bool "TPL requires early-return (for RK3188-style BROM) to BROM"
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depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
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help
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Some Rockchip BROM variants (e.g. on the RK3188) load the
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first stage in segments and enter multiple times. E.g. on
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the RK3188, the first 1KB of the first stage are loaded
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first and entered; after returning to the BROM, the
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remainder of the first stage is loaded, but the BROM
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re-enters at the same address/to the same code as previously.
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This enables support code in the BOOT0 hook for the TPL stage
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to allow multiple entries.
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config SPL_MMC_SUPPORT
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default y if !SPL_ROCKCHIP_BACK_TO_BROM
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source "arch/arm/mach-rockchip/rk3036/Kconfig"
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source "arch/arm/mach-rockchip/rk3188/Kconfig"
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source "arch/arm/mach-rockchip/rk322x/Kconfig"
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source "arch/arm/mach-rockchip/rk3288/Kconfig"
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source "arch/arm/mach-rockchip/rk3328/Kconfig"
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source "arch/arm/mach-rockchip/rk3368/Kconfig"
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source "arch/arm/mach-rockchip/rk3399/Kconfig"
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source "arch/arm/mach-rockchip/rv1108/Kconfig"
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endif
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