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u-boot/board/stxssa
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Dave Liu b4983e16d1 fsl-ddr: use the 1T timing as default configuration 
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-01-23 17:03:14 -06:00
..
config.mk Add support for STX GP3SSA (stxssa) Board with 4 MiB flash. 2007-05-31 17:20:09 +02:00
ddr.c fsl-ddr: use the 1T timing as default configuration 2009-01-23 17:03:14 -06:00
law.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
Makefile FSL DDR: Convert STXSSA to new DDR code. 2008-08-27 11:43:53 -05:00
stxssa.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
tlb.c rename CFG_ macros to CONFIG_SYS 2008-10-18 21:54:03 +02:00
u-boot.lds Align end of bss by 4 bytes 2008-11-18 23:13:16 +01:00