Rick Chen 52923c6db7 riscv: cache: Implement i/dcache [status, enable, disable] ... AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>		2018-11-26 13:58:01 +08:00
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cpu	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
dts	riscv: dts: Add ae350_32.dts for RV32I	2018-11-26 13:57:55 +08:00
include/asm	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
lib	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
config.mk	riscv: enable -fdata-sections	2018-11-26 13:57:29 +08:00
Kconfig	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
Makefile	riscv: set -march and -mabi based on the Kconfig configuration	2018-11-26 13:57:29 +08:00