mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
4684a7a43a
Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
715 lines
14 KiB
C
715 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <misc.h>
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#include <net.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/list.h>
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#include <asm/arch/board.h>
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#include <asm/io.h>
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#include "cgx_intf.h"
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#include "cgx.h"
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#include "nix.h"
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static u64 cgx_rd_scrx(u8 cgx, u8 lmac, u8 index)
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{
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u64 addr;
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addr = (index == 1) ? CGX_CMR_SCRATCH1 : CGX_CMR_SCRATCH0;
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addr += CGX_SHIFT(cgx) + CMR_SHIFT(lmac);
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return readq(addr);
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}
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static void cgx_wr_scrx(u8 cgx, u8 lmac, u8 index, u64 val)
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{
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u64 addr;
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addr = (index == 1) ? CGX_CMR_SCRATCH1 : CGX_CMR_SCRATCH0;
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addr += CGX_SHIFT(cgx) + CMR_SHIFT(lmac);
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writeq(val, addr);
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}
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static u64 cgx_rd_scr0(u8 cgx, u8 lmac)
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{
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return cgx_rd_scrx(cgx, lmac, 0);
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}
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static u64 cgx_rd_scr1(u8 cgx, u8 lmac)
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{
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return cgx_rd_scrx(cgx, lmac, 1);
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}
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static void cgx_wr_scr0(u8 cgx, u8 lmac, u64 val)
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{
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return cgx_wr_scrx(cgx, lmac, 0, val);
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}
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static void cgx_wr_scr1(u8 cgx, u8 lmac, u64 val)
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{
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return cgx_wr_scrx(cgx, lmac, 1, val);
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}
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static inline void set_ownership(u8 cgx, u8 lmac, u8 val)
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{
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union cgx_scratchx1 scr1;
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scr1.u = cgx_rd_scr1(cgx, lmac);
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scr1.s.own_status = val;
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cgx_wr_scr1(cgx, lmac, scr1.u);
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}
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static int wait_for_ownership(u8 cgx, u8 lmac)
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{
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union cgx_scratchx1 scr1;
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union cgx_scratchx0 scr0;
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u64 cmrx_int;
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int timeout = 5000;
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do {
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scr1.u = cgx_rd_scr1(cgx, lmac);
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scr0.u = cgx_rd_scr0(cgx, lmac);
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/* clear async events if any */
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if (scr0.s.evt_sts.evt_type == CGX_EVT_ASYNC &&
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scr0.s.evt_sts.ack) {
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/* clear interrupt */
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cmrx_int = readq(CGX_CMR_INT +
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CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
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cmrx_int |= 0x2; // Overflw bit
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writeq(cmrx_int, CGX_CMR_INT +
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CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
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/* clear ack */
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scr0.s.evt_sts.ack = 0;
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cgx_wr_scr0(cgx, lmac, scr0.u);
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}
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if (timeout-- < 0) {
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debug("timeout waiting for ownership\n");
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return -ETIMEDOUT;
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}
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mdelay(1);
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} while ((scr1.s.own_status == CGX_OWN_FIRMWARE) &&
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scr0.s.evt_sts.ack);
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return 0;
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}
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int cgx_intf_req(u8 cgx, u8 lmac, union cgx_cmd_s cmd_args, u64 *rsp,
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int use_cmd_id_only)
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{
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union cgx_scratchx1 scr1;
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union cgx_scratchx0 scr0;
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u64 cmrx_int;
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int timeout = 500;
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int err = 0;
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u8 cmd = cmd_args.cmd.id;
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if (wait_for_ownership(cgx, lmac)) {
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err = -ETIMEDOUT;
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goto error;
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}
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/* send command */
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scr1.u = cgx_rd_scr1(cgx, lmac);
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if (use_cmd_id_only) {
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scr1.s.cmd.id = cmd;
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} else {
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cmd_args.own_status = scr1.s.own_status;
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scr1.s = cmd_args;
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}
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cgx_wr_scr1(cgx, lmac, scr1.u);
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set_ownership(cgx, lmac, CGX_OWN_FIRMWARE);
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/* wait for response and ownership */
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do {
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scr0.u = cgx_rd_scr0(cgx, lmac);
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scr1.u = cgx_rd_scr1(cgx, lmac);
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mdelay(10);
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} while (timeout-- && (!scr0.s.evt_sts.ack) &&
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(scr1.s.own_status == CGX_OWN_FIRMWARE));
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if (timeout < 0) {
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debug("%s timeout waiting for ack\n", __func__);
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err = -ETIMEDOUT;
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goto error;
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}
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if (cmd == CGX_CMD_INTF_SHUTDOWN)
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goto error;
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if (scr0.s.evt_sts.evt_type != CGX_EVT_CMD_RESP) {
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debug("%s received async event instead of cmd resp event\n",
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__func__);
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err = -1;
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goto error;
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}
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if (scr0.s.evt_sts.id != cmd) {
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debug("%s received resp for cmd %d expected cmd %d\n",
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__func__, scr0.s.evt_sts.id, cmd);
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err = -1;
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goto error;
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}
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if (scr0.s.evt_sts.stat != CGX_STAT_SUCCESS) {
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debug("%s cmd%d failed on cgx%u lmac%u with errcode %d\n",
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__func__, cmd, cgx, lmac, scr0.s.link_sts.err_type);
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err = -1;
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}
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error:
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/* clear interrupt */
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cmrx_int = readq(CGX_CMR_INT + CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
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cmrx_int |= 0x2; // Overflw bit
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writeq(cmrx_int, CGX_CMR_INT + CGX_SHIFT(cgx) + CMR_SHIFT(lmac));
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/* clear ownership and ack */
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scr0.s.evt_sts.ack = 0;
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cgx_wr_scr0(cgx, lmac, scr0.u);
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*rsp = err ? 0 : scr0.u;
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return err;
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}
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int cgx_intf_get_mac_addr(u8 cgx, u8 lmac, u8 *mac)
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{
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_GET_MAC_ADDR;
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ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
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if (ret)
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return -1;
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scr0.u >>= 9;
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memcpy(mac, &scr0.u, 6);
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return 0;
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}
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int cgx_intf_get_ver(u8 cgx, u8 lmac, u8 *ver)
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{
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_GET_FW_VER;
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ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
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if (ret)
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return -1;
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scr0.u >>= 9;
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*ver = scr0.u & 0xFFFF;
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return 0;
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}
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int cgx_intf_get_link_sts(u8 cgx, u8 lmac, u64 *lnk_sts)
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{
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_GET_LINK_STS;
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ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
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if (ret)
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return -1;
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scr0.u >>= 9;
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/* pass the same format as cgx_lnk_sts_s
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* err_type:10, speed:4, full_duplex:1, link_up:1
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*/
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*lnk_sts = scr0.u & 0xFFFF;
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return 0;
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}
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int cgx_intf_link_up_dwn(u8 cgx, u8 lmac, u8 up_dwn, u64 *lnk_sts)
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{
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = up_dwn ? CGX_CMD_LINK_BRING_UP : CGX_CMD_LINK_BRING_DOWN;
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ret = cgx_intf_req(cgx, lmac, cmd, &scr0.u, 1);
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if (ret)
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return -1;
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scr0.u >>= 9;
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/* pass the same format as cgx_lnk_sts_s
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* err_type:10, speed:4, full_duplex:1, link_up:1
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*/
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*lnk_sts = scr0.u & 0xFFFF;
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return 0;
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}
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void cgx_intf_shutdown(void)
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{
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union cgx_scratchx0 scr0;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_INTF_SHUTDOWN;
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cgx_intf_req(0, 0, cmd, &scr0.u, 1);
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}
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int cgx_intf_prbs(u8 qlm, u8 mode, u32 time, u8 lane)
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{
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_PRBS;
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cmd.prbs_args.qlm = qlm;
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cmd.prbs_args.mode = mode;
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cmd.prbs_args.time = time;
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cmd.prbs_args.lane = lane;
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ret = cgx_intf_req(0, 0, cmd, &scr0.u, 0);
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if (ret)
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return -1;
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return 0;
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}
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enum cgx_mode {
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MODE_10G_C2C,
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MODE_10G_C2M,
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MODE_10G_KR,
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MODE_25G_C2C,
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MODE_25G_2_C2C,
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MODE_50G_C2C,
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MODE_50G_4_C2C
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};
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static char intf_speed_to_str[][8] = {
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"10M",
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"100M",
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"1G",
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"2.5G",
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"5G",
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"10G",
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"20G",
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"25G",
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"40G",
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"50G",
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"80G",
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"100G",
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};
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static void mode_to_args(int mode, struct cgx_mode_change_args *args)
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{
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args->an = 0;
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args->duplex = 0;
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args->port = 0;
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switch (mode) {
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case MODE_10G_C2C:
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args->speed = CGX_LINK_10G;
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args->mode = BIT_ULL(CGX_MODE_10G_C2C_BIT);
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break;
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case MODE_10G_C2M:
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args->speed = CGX_LINK_10G;
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args->mode = BIT_ULL(CGX_MODE_10G_C2M_BIT);
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break;
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case MODE_10G_KR:
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args->speed = CGX_LINK_10G;
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args->mode = BIT_ULL(CGX_MODE_10G_KR_BIT);
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args->an = 1;
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break;
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case MODE_25G_C2C:
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args->speed = CGX_LINK_25G;
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args->mode = BIT_ULL(CGX_MODE_25G_C2C_BIT);
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break;
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case MODE_25G_2_C2C:
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args->speed = CGX_LINK_25G;
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args->mode = BIT_ULL(CGX_MODE_25G_2_C2C_BIT);
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break;
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case MODE_50G_C2C:
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args->speed = CGX_LINK_50G;
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args->mode = BIT_ULL(CGX_MODE_50G_C2C_BIT);
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break;
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case MODE_50G_4_C2C:
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args->speed = CGX_LINK_50G;
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args->mode = BIT_ULL(CGX_MODE_50G_4_C2C_BIT);
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}
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}
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int cgx_intf_set_mode(struct udevice *ethdev, int mode)
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{
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struct rvu_pf *rvu = dev_get_priv(ethdev);
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struct nix *nix = rvu->nix;
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_MODE_CHANGE;
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mode_to_args(mode, &cmd.mode_change_args);
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ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
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cmd, &scr0.u, 0);
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if (ret) {
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printf("Mode change command failed for %s\n", ethdev->name);
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return -1;
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}
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cmd.cmd.id = CGX_CMD_GET_LINK_STS;
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ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
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cmd, &scr0.u, 1);
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if (ret) {
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printf("Get Link Status failed for %s\n", ethdev->name);
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return -1;
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}
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printf("Current Link Status: ");
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if (scr0.s.link_sts.speed) {
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printf("%s\n", intf_speed_to_str[scr0.s.link_sts.speed]);
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switch (scr0.s.link_sts.fec) {
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case 0:
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printf("FEC_NONE\n");
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break;
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case 1:
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printf("FEC_BASE_R\n");
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break;
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case 2:
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printf("FEC_RS\n");
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break;
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}
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printf("Auto Negotiation %sabled\n",
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scr0.s.link_sts.an ? "En" : "Dis");
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printf("%s Duplex\n",
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scr0.s.link_sts.full_duplex ? "Full" : "Half");
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} else {
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printf("Down\n");
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}
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return 0;
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}
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int cgx_intf_get_mode(struct udevice *ethdev)
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{
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struct rvu_pf *rvu = dev_get_priv(ethdev);
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struct nix *nix = rvu->nix;
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_GET_LINK_STS;
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ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
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cmd, &scr0.u, 1);
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if (ret) {
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printf("Get link status failed for %s\n", ethdev->name);
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return -1;
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}
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printf("Current Interface Mode: ");
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switch (scr0.s.link_sts.mode) {
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case CGX_MODE_10G_C2C_BIT:
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printf("10G_C2C\n");
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break;
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case CGX_MODE_10G_C2M_BIT:
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printf("10G_C2M\n");
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break;
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case CGX_MODE_10G_KR_BIT:
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printf("10G_KR\n");
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break;
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case CGX_MODE_25G_C2C_BIT:
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printf("25G_C2C\n");
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break;
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case CGX_MODE_25G_2_C2C_BIT:
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printf("25G_2_C2C\n");
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break;
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case CGX_MODE_50G_C2C_BIT:
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printf("50G_C2C\n");
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break;
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case CGX_MODE_50G_4_C2C_BIT:
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printf("50G_4_C2C\n");
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break;
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default:
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printf("Unknown\n");
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break;
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}
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return 0;
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}
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int cgx_intf_get_fec(struct udevice *ethdev)
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{
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struct rvu_pf *rvu = dev_get_priv(ethdev);
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struct nix *nix = rvu->nix;
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union cgx_scratchx0 scr0;
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int ret;
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union cgx_cmd_s cmd;
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cmd.cmd.id = CGX_CMD_GET_SUPPORTED_FEC;
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ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
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cmd, &scr0.u, 1);
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if (ret) {
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printf("Get supported FEC failed for %s\n", ethdev->name);
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return -1;
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}
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printf("Supported FEC type: ");
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switch (scr0.s.supported_fec.fec) {
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case 0:
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printf("FEC_NONE\n");
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break;
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case 1:
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printf("FEC_BASE_R\n");
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break;
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case 2:
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printf("FEC_RS\n");
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break;
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case 3:
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printf("FEC_BASE_R FEC_RS\n");
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break;
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}
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cmd.cmd.id = CGX_CMD_GET_LINK_STS;
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ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
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cmd, &scr0.u, 1);
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if (ret) {
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printf("Get active fec failed for %s\n", ethdev->name);
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return -1;
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}
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printf("Active FEC type: ");
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switch (scr0.s.link_sts.fec) {
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case 0:
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printf("FEC_NONE\n");
|
|
break;
|
|
case 1:
|
|
printf("FEC_BASE_R\n");
|
|
break;
|
|
case 2:
|
|
printf("FEC_RS\n");
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_set_fec(struct udevice *ethdev, int type)
|
|
{
|
|
struct rvu_pf *rvu = dev_get_priv(ethdev);
|
|
struct nix *nix = rvu->nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
|
|
cmd.cmd.id = CGX_CMD_SET_FEC;
|
|
cmd.fec_args.fec = type;
|
|
|
|
ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
|
|
cmd, &scr0.u, 0);
|
|
if (ret) {
|
|
printf("Set FEC type %d failed for %s\n", type, ethdev->name);
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_get_phy_mod_type(struct udevice *ethdev)
|
|
{
|
|
struct rvu_pf *rvu = dev_get_priv(ethdev);
|
|
struct nix *nix = rvu->nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
|
|
cmd.cmd.id = CGX_CMD_GET_PHY_MOD_TYPE;
|
|
|
|
ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
|
|
cmd, &scr0.u, 1);
|
|
if (ret) {
|
|
printf("Get PHYMOD type failed for %s\n", ethdev->name);
|
|
return -1;
|
|
}
|
|
printf("Current phy mod type %s\n",
|
|
scr0.s.phy_mod_type.mod ? "PAM4" : "NRZ");
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_set_phy_mod_type(struct udevice *ethdev, int type)
|
|
{
|
|
struct rvu_pf *rvu = dev_get_priv(ethdev);
|
|
struct nix *nix = rvu->nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
|
|
cmd.cmd.id = CGX_CMD_SET_PHY_MOD_TYPE;
|
|
cmd.phy_mod_args.mod = type;
|
|
|
|
ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
|
|
cmd, &scr0.u, 0);
|
|
if (ret) {
|
|
printf("Set PHYMOD type %d failed for %s\n", type,
|
|
ethdev->name);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_set_an_lbk(struct udevice *ethdev, int enable)
|
|
{
|
|
struct rvu_pf *rvu = dev_get_priv(ethdev);
|
|
struct nix *nix = rvu->nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
|
|
cmd.cmd.id = CGX_CMD_AN_LOOPBACK;
|
|
cmd.cmd_args.enable = enable;
|
|
|
|
ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
|
|
cmd, &scr0.u, 0);
|
|
if (ret) {
|
|
printf("Set AN loopback command failed on %s\n", ethdev->name);
|
|
return -1;
|
|
}
|
|
printf("AN loopback %s for %s\n", enable ? "set" : "clear",
|
|
ethdev->name);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_get_ignore(struct udevice *ethdev, int cgx, int lmac)
|
|
{
|
|
struct rvu_pf *rvu;
|
|
struct nix *nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret, cgx_id = cgx, lmac_id = lmac;
|
|
union cgx_cmd_s cmd;
|
|
|
|
if (ethdev) {
|
|
rvu = dev_get_priv(ethdev);
|
|
nix = rvu->nix;
|
|
cgx_id = nix->lmac->cgx->cgx_id;
|
|
lmac_id = nix->lmac->lmac_id;
|
|
}
|
|
cmd.cmd.id = CGX_CMD_GET_PERSIST_IGNORE;
|
|
|
|
ret = cgx_intf_req(cgx_id, lmac_id, cmd, &scr0.u, 1);
|
|
if (ret) {
|
|
if (ethdev)
|
|
printf("Get ignore command failed for %s\n",
|
|
ethdev->name);
|
|
else
|
|
printf("Get ignore command failed for CGX%d LMAC%d\n",
|
|
cgx_id, lmac_id);
|
|
return -1;
|
|
}
|
|
if (ethdev)
|
|
printf("Persist settings %signored for %s\n",
|
|
scr0.s.persist.ignore ? "" : "not ", ethdev->name);
|
|
else
|
|
printf("Persist settings %signored for CGX%d LMAC%d\n",
|
|
scr0.s.persist.ignore ? "" : "not ", cgx_id, lmac_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_set_ignore(struct udevice *ethdev, int cgx, int lmac, int ignore)
|
|
{
|
|
struct rvu_pf *rvu;
|
|
struct nix *nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret, cgx_id = cgx, lmac_id = lmac;
|
|
union cgx_cmd_s cmd;
|
|
|
|
if (ethdev) {
|
|
rvu = dev_get_priv(ethdev);
|
|
nix = rvu->nix;
|
|
cgx_id = nix->lmac->cgx->cgx_id;
|
|
lmac_id = nix->lmac->lmac_id;
|
|
}
|
|
cmd.cmd.id = CGX_CMD_SET_PERSIST_IGNORE;
|
|
cmd.persist_args.ignore = ignore;
|
|
|
|
ret = cgx_intf_req(cgx_id, lmac_id, cmd, &scr0.u, 0);
|
|
if (ret) {
|
|
if (ethdev)
|
|
printf("Set ignore command failed for %s\n",
|
|
ethdev->name);
|
|
else
|
|
printf("Set ignore command failed for CGX%d LMAC%d\n",
|
|
cgx_id, lmac_id);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_set_macaddr(struct udevice *ethdev)
|
|
{
|
|
struct rvu_pf *rvu = dev_get_priv(ethdev);
|
|
struct nix *nix = rvu->nix;
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
u64 mac, tmp;
|
|
|
|
memcpy((void *)&tmp, nix->lmac->mac_addr, 6);
|
|
mac = swab64(tmp) >> 16;
|
|
cmd.cmd.id = CGX_CMD_SET_MAC_ADDR;
|
|
cmd.mac_args.addr = mac;
|
|
cmd.mac_args.pf_id = rvu->pfid;
|
|
|
|
ret = cgx_intf_req(nix->lmac->cgx->cgx_id, nix->lmac->lmac_id,
|
|
cmd, &scr0.u, 0);
|
|
if (ret) {
|
|
printf("Set user mac addr failed for %s\n", ethdev->name);
|
|
return -1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_display_eye(u8 qlm, u8 lane)
|
|
{
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
|
|
cmd.cmd.id = CGX_CMD_DISPLAY_EYE;
|
|
|
|
cmd.dsp_eye_args.qlm = qlm;
|
|
cmd.dsp_eye_args.lane = lane;
|
|
|
|
ret = cgx_intf_req(0, 0, cmd, &scr0.u, 0);
|
|
if (ret)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int cgx_intf_display_serdes(u8 qlm, u8 lane)
|
|
{
|
|
union cgx_scratchx0 scr0;
|
|
int ret;
|
|
union cgx_cmd_s cmd;
|
|
|
|
cmd.cmd.id = CGX_CMD_DISPLAY_SERDES;
|
|
|
|
cmd.dsp_eye_args.qlm = qlm;
|
|
cmd.dsp_eye_args.lane = lane;
|
|
|
|
ret = cgx_intf_req(0, 0, cmd, &scr0.u, 0);
|
|
if (ret)
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|