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61a21e980a
From: Ed Swarthout <Ed.Swarthout@freescale.com> Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
64 lines
2.4 KiB
C
64 lines
2.4 KiB
C
/*
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* Copyright 2004, 2007 Freescale Semiconductor.
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* Copyright(c) 2003 Motorola Inc.
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*/
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#ifndef __MPC85xx_H__
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#define __MPC85xx_H__
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/* define for common ppc_asm.tmpl */
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#define EXC_OFF_SYS_RESET 0x100 /* System reset */
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#define _START_OFFSET 0
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#if defined(CONFIG_E500)
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#include <e500.h>
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#endif
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/*
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* SCCR - System Clock Control Register, 9-8
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*/
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#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
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#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
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#define SCCR_DFBRG_SHIFT 0
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#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
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#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
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#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
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#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
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/*
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* Local Bus Controller - memory controller registers
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*/
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#define BRx_V 0x00000001 /* Bank Valid */
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#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
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#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */
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#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
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#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
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#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
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#define BRx_PS_8 0x00000800 /* 8 bit port size */
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#define BRx_PS_32 0x00001800 /* 32 bit port size */
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#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
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#define ORxG_EAD 0x00000001 /* External addr latch delay */
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#define ORxG_EHTR 0x00000002 /* Extended hold time on read */
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#define ORxG_TRLX 0x00000004 /* Timing relaxed */
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#define ORxG_SETA 0x00000008 /* External address termination */
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#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
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#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
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#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */
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#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
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#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
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#define ORxU_BI 0x00000100 /* Burst Inhibit */
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#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
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#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
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#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
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#define MxMR_OP_WARR 0x10000000 /* Write to Array */
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#define MxMR_BSEL 0x80000000 /* Bus Select */
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/* helpers to convert values into an OR address mask (GPCM mode) */
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#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
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#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
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#endif /* __MPC85xx_H__ */
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